Leakage-tolerant circuit and method for large register files
AssigneeIntel Corporation
InventorsAtila Alvandpour, Ganesh Balamurugan, Krishnamurthy Soumyanath
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Abstract
A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.
Claims18
A method for reducing leakage current in a register file cell comprising forcing a negative gate-source voltage on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced.
A low leakage register file cell comprising:
- a cell read transistor;
- a critical pass transistor coupled between the cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from the cell read transistor is reduced.
A low leakage register file system comprising:
- a local bitline;
- a first input coupled to the bitline, the first input issuing control signals o control the file system;
- a plurality of cells coupled to the bitline, each cell comprising;
- a cell read transistor;
- a critical pass transistor coupled between the cell read transistor and the local bitline such that when the cell is in a first state, the leakage current from the cell read transistor is reduced.
An apparatus for reducing leakage current in a register file cell comprising:
- a critical pass transistor means coupled between a cell read transistor and a local bitline;
- and
- means for forcing a negative gate-source voltage on the critical pass transistor means such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced.
Dependencies are inferred from the claim text.