Dual port sram

A dual port memory comprising:

• means for storing information configured to (i) write information to a first port or (ii) read information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals;
• means for generating one or more first control signals in response to one or more first address signals;
• means for generating one or more second control signals in response to one or more second address signals;
• means for generating said one or more first timing signals and said one or more second timing signals in response to said one or more first control signals and said one or more second control signals;
• means for multiplexing read and write information at one or more first pins in response to one or more of said timing signals;
• and
• means for multiplexing read and write information at one or more second pins in response to one or more of said timing signals.

A method for reading and writing information to a memory comprising the steps of:

• (A) writing information to a first port or (ii) reading information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals;
• (B) generating one or more first control signals in response to one or more first address signals;
• (C) generating one or more second control signals in response to one or more second address signals;
• (D) generating said one or more first timing signals and said one or more second timing signals in response to said one or more first control signals and said one or more second control signals;
• (E) multiplexing said information at one or more first pins in response to one or more of said timing signals;
• and
• (F) multiplexing said information at one or more second pins in response to one or more of said timing signals.