US 6,388,938 B2 · Semiconductor memory device

Abstract

There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . . , n−1) output selection control part receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the first cell array via the 2i-th output signal line, the n-th output selection control part receiving the output of the (2n−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2n−1)-th output signal line and receiving the output of the auxiliary input/output part of each of the section parts of the first cell array via the 2n-th output signal line, and the (n+i)-th (i=1, . . . , n−1) output control circuit receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i)-th output signal line.

Claims2

Dependent claims

A semiconductor memory device comprising:

first and second cell arrays, each of which has the same number of memory cells;
first through (2n−1)-th (n≧1) output selection control circuits;
first through (2n−1)-th output transistor circuits which are provided so as to correspond to said first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of said output transistor circuits;
and
first through (4n−2)-th output signal lines,
each of said first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part,
said i-th (i=1, . . . , n−1) output selection control part receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of said first cell array via the (2i−1)-th output signal line, and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of said first cell array via the 2i-th output signal line,
said n-th output selection control part receiving the output of the (2n−1)-th input/output part of each of the first through k-th section parts of said first cell array via the (2n−1)-th output signal line, and receiving the output of the auxiliary input/output part of each of said section parts of said first cell array via the 2n-th output signal line, and
said (n+i)-th (i=1, . . . , n−1) output control circuit receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of said second cell array via the (2n+2i−1)-th output signal line, and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of said second cell array via the (2n+2i)-th output signal line.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims2