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AssigneeOki Electric Industry Co., Ltd.
InventorsMasakuni Kawagoe, Norihiko Satani, Yoshihiro Nakatake, Akihiro Narumi
Estimating the term…
A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory 10 is provided with a plurality of output circuits 11 and a fuse circuit 12 connected to each of the output circuits. The fuse circuit outputs output signals N1 and N2 to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f1 and f2 in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit 112 and a pre-driver circuit unit 111 that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit. By providing the fuses that can be easily disconnected with a laser beam, it becomes possible to adjacent the gate widths of the pre-drivers at the plurality of output circuit units all at once. As a result, the length of machining time can be reduced compared to that required in the prior art technology.
A semiconductor memory, comprising:
A semiconductor memory, comprising:
A semiconductor memory, comprising:
A semiconductor memory, comprising:
A semiconductor memory, comprising:
A semiconductor memory, comprising:
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Dependencies are inferred from the claim text.