Semiconductor memory device operating at high speed with low current consumption

A semiconductor memory device including:

• a plurality of memory cells arranged in rows and columns;
• a plurality of normal bit line pairs, provided corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column and including first and second normal bit lines;
• a plurality of refresh bit line pairs, provided corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column and including first and second refresh bit lines;
• each of said plurality of memory cells including a first transistor connected between one of said first and second normal bit lines of a corresponding normal bit line pair and a storage node, a capacitor connected between said storage node and a constant voltage source, and a second transistor connected between said storage node and one of said first and second refresh bit lines of the corresponding column;
• a plurality of normal word lines, provided corresponding to the rows of memory cells, each connecting to the first transistors of the memory cells on a corresponding row;
• a plurality of refresh word lines, provided corresponding to the rows of memory cells, each connecting to the second transistors of the memory cells on a corresponding row;
• refresh row select circuitry for selecting an addressed refresh word line of said plurality of refresh word lines in accordance with a refresh address;
• normal row select circuitry for selecting an addressed normal word line of said plurality of normal word lines in accordance with an external address;
• determining circuitry for determining whether said refresh address and said external address are coincide with each other;
• a comparator for comparing activation timings of a refresh requesting signal and a memory cell select cycle start instructing signal;
• and
• access circuitry for performing data access through a refresh bit line pair when said determining circuitry detects coincidence and said comparator indicates that activation of said refresh requesting signal is earlier.