Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
AssigneeMicron Technology, Inc.
InventorJames W. Wilkins
Life of this patent
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Abstract
A dummy wordline in a semiconductor memory controls the timing of the firing of sense amplifiers in the memory in relation to the firing of active wordlines in the memory. The dummy wordline receives a timing signal at the same time that an active wordline is fired, and the length of the dummy wordline is set during fabrication so the timing signal propagating along the dummy wordline arrives at the sense amplifiers and fires the sense amplifiers at a desired time.
Claims20
An apparatus in a semiconductor memory for controlling timing of firing of column selection and sensing circuitry in the semiconductor memory, the apparatus comprising a dummy wordline fabricated within an array of memory cells in the semiconductor memory;
- the dummy wordline including a first leg and a second leg coupled by a shunt selectively positioned between the first leg and the second leg to define a selected length for the dummy wordline to delay a timing signal traversing the dummy wordline by a selected amount of time before the timing signal fires the column selection and sensing circuitry.
A semiconductor memory comprising:
- address buffers;
- address decoders coupled to the address buffers;
- wordline selection and driving circuitry coupled to the address decoders;
- active wordlines coupled to the wordline selection and driving circuitry;
- an array of memory cells coupled to the active wordlines;
- bitlines coupled to the array of memory cells;
- column selection and sensing circuitry coupled to the bitlines and the address decoders;
- output circuitry coupled to the column selection and sensing circuitry;
- and
- a dummy wordline coupled between the wordline selection and driving circuitry and the column selection and sensing circuitry and fabricated within the array of memory cells;
- the dummy wordline including a first leg and a second leg coupled by a shunt selectively positioned between the first leg and the second leg to define a selected length for the dummy wordline to delay, by a selected amount of time, a timing signal received from the wordline selection and driving circuitry that traverses the length of the dummy wordline before firing the column selection and sensing circuitry.
An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory comprising:
- address buffers;
- address decoders coupled to the address buffers;
- wordline selection and driving circuitry coupled to the address decoders;
- active wordlines coupled to the wordline selection and driving circuitry;
- an array of memory cells coupled to the active wordlines;
- bitlines coupled to the array of memory cells;
- column selection and sensing circuitry coupled to the bitlines and the address decoders;
- output circuitry coupled to the column selection and sensing circuitry;
- and
- a dummy wordline coupled between the wordline selection and driving circuitry and the column selection and sensing circuitry and fabricated within the array of memory cells with a length selected to delay, by a selected amount of time, a timing signal received from the wordline selection and driving circuitry that traverses the length of the dummy wordline before firing the column selection and sensing circuitry.
A semiconductor wafer on which is fabricated a semiconductor memory that comprises:
- address buffers;
- address decoders coupled to the address buffers;
- wordline selection and driving circuitry coupled to the address decoders;
- active wordlines coupled to the wordline selection and driving circuitry;
- an array of memory cells coupled to the active wordlines;
- bitlines coupled to the array of memory cells;
- column selection and sensing circuitry coupled to the bitlines and the address decoders;
- output circuitry coupled to the column selection and sensing circuitry;
- and
- a dummy wordline coupled between the wordline selection and driving circuitry and the column selection and sensing circuitry and fabricated within the array of memory cells with a length selected to delay, by a selected amount of time, a timing signal received from the wordline selection and driving circuitry that traverses the length of the dummy wordline before firing the column selection and sensing circuitry.
A method for controlling timing of a firing of column selection and sensing circuitry in a semiconductor memory, the method comprising:
- generating a timing signal for firing the column selection and sensing circuitry;
- delaying arrival of the timing signal at the column selection and sensing circuitry by impeding conduction of the timing signal to the column selection and sensing circuitry using a dummy wordline fabricated within an array of memory cells in the semiconductor memory with a length defined by a shunt coupled between a first leg and a second leg of the dummy wordline and selectively positioned between the first leg and the second leg to define an amount of time by which the timing signal is delayed, and the dummy wordline having impedance characteristics that are substantially the same as impedance characteristics of an active wordline traversing an array of memory cells in the semiconductor memory;
- and
- firing the column selection and sensing circuitry using the delayed timing signal.
A method for controlling timing of a firing of column selection and sensing circuitry in a semiconductor memory, the method comprising:
- generating a timing signal for firing the column selection and sensing circuitry;
- delaying arrival of the timing signal at the column selection and sensing circuitry using a dummy wordline fabricated within an array of memory cells in the semiconductor memory with a length defined by coupling a first leg and a second leg of the dummy wordline with a shunt selectively positioned between the first leg and the second leg to define an amount of time by which the timing signal is delayed;
- and
- firing the column selection and sensing circuitry using the delayed timing signal.
Dependencies are inferred from the claim text.