Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters
AssigneeInternational Business Machines Corporation
InventorThomas E. Obremski
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Abstract
A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.
Claims20
A method for generating a selected subset of memory addresses associated with a semiconductor memory array, the method comprising:
- configuring an address counter to generate addresses corresponding to locations within the memory array;
- and
- programming a mask register with a series of masking bits, the value of said masking bits determining whether corresponding address bits in said address counter are masked or not masked;
- wherein any of said address bits in said address counter corresponding to a masked bit are masked from a counting operation performed by said address counter, thereby causing said address counter to generate the selected subset of memory addresses.
A method for testing a semiconductor memory array having a built-in self test (BIST) device embedded therein, the method comprising:
- configuring an address counter within the BIST device to generate addresses corresponding to locations within the memory array;
- and
- programming a mask register with a series of masking bits, the value of said masking bits determining whether corresponding address bits in said address counter are masked or not masked;
- wherein any of said address bits in said address counter corresponding to a masked bit are masked from a counting operation performed by said address counter, thereby allowing only a desired subset of the semiconductor memory array to be tested by the BIST unit.
An apparatus for testing selected addresses of a semiconductor memory array, comprising:
- a built-in self test (BIST) device including an address counter for generating test address signals representing semiconductor array locations to be tested;
- and
- a mask register for selectively masking specific bit positions in said address counter, said mask register containing a series of programmed masking bits therein, the value of said masking bits determining whether corresponding address bits in said address counter are masked or not masked;
- wherein any of said address bits in said address counter corresponding to a masked bit are masked from a counting operation performed by said address counter, thereby allowing only a desired subset of the semiconductor memory array to be tested by said BIST device.
Dependencies are inferred from the claim text.