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US 6,388,929 B1Granted
Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroki Shimano, Kazutami Arimoto
Life of this patent
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Abstract
A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.
Claims18
A semiconductor memory device for inputting/outputting data in accordance with an input address, comprising:
- a memory cell array for storing said data by a plurality of regular memory cells and spare memory cells;
- a self test circuit for conducting an operation test on said memory cell array to detect a defective memory cell,
- said self test circuit including
- a self test control unit for activating said operation test at predetermined time, and
- a redundancy repair analyzing unit for analyzing data outputted from said memory cell array in said operation test and outputting a plurality of redundancy code signals for indicating a defect address corresponding to said defective memory cell;
- and
- a decoding circuit for selecting a memory cell as a target of data input and output in accordance with said input address,
- said decoding circuit including
- a repair determining circuit for instructing an access to said spare memory cell when said input address and said defect address coincide with each other,
- said repair determining circuit having a plurality of redundancy code holding circuits provided in correspondence with said plurality of redundancy code signals, and
- each of said plurality of redundancy code holding circuits taking in a signal level of a corresponding one of said plurality of redundancy code signals outputted from said redundancy repair analyzing unit in said operation test and holding the taken signal level.
8 more elements
A semiconductor integrated circuit device comprising:
- a plurality of memory cores each for executing data input and output according to an input address,
- each of said plurality of memory cores including
- a memory cell array for storing data by a plurality of regular memory cells and a spare memory cell used to be replaced with a defective memory cell, and
- a decoding circuit for selecting a memory cell as a target of the data input and output in accordance with said input address,
- said decoding circuit including a repair determining circuit for instructing an access to said spare memory cell when said input address and a defect address corresponding to said defective memory cell coincide with each other,
- said repair determining circuit having a plurality of redundancy code holding circuits provided in correspondence with a plurality of redundancy code signals for indicating said defect address,
- each of said plurality of redundancy code holding circuits taking in a signal level of a corresponding one of said plurality of redundancy code signals in a operation test to detect said defective memory cell and holding the taken signal level;
- a self test circuit which is shared by said plurality of memory cores and conducts said operation test on said memory cell array,
- said self test circuit including
- a self test control unit for activating said operation test, and
- a redundancy repair analyzing unit for analyzing data outputted from said memory cell array in said operation test and outputting said plurality of redundancy code signals;
- a selection control circuit for selecting one of said plurality of memory cores;
- and
- a selector circuit provided between said plurality of memory cores and said self test circuit for coupling said one of the plurality of memory. cores and said self test circuit in accordance with selection by said selection control circuit.
11 more elements
A semiconductor memory device for inputting/outputting data in accordance with an input address, comprising:
- a memory cell array for storing data by a plurality of regular memory cells and a plurality of spare memory units;
- a program unit for storing, in a non-volatile manner, redundancy information for indicating an address of a defect corresponding to a preliminarily detected defective memory cell;
- a self test circuit for conducting an operation test to detect said defective memory cell to said memory cell array,
- the self test circuit including
- a self test control unit for activating said operation test at predetermined time, and
- a redundancy repair analyzing unit for analyzing data outputted from said memory cell array in said operation test and outputting redundancy information for indicating a defect address corresponding to a defective memory cell detected by said operation test;
- a control unit for instructing each of said program unit and said redundancy repair analyzing unit to output said redundancy information;
- and
- a decoding circuit for selecting a memory cell as a target of said data input and output in accordance with said input address,
- said decoding circuit including a plurality of repair determining circuits provided for said plurality of spare memory units, and
- each of said plurality of repair determining circuits storing one of said redundancy information outputted from said program unit and said redundancy repair analyzing unit and instructing an access to a corresponding one of said plurality of spare memory units when said defect address corresponding to said redundancy information stored coincides with said input address.
8 more elements
Dependencies are inferred from the claim text.