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US 6,388,928 B1Granted
Method and system for reduction of test time for analog chip manufacturing
AssigneeSummit Microelectronics, Inc.
InventorsTheodore M. Myers, Richard V. Orlando
Life of this patent
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Abstract
Analog integrated circuits have their individual characteristics compensated by the settings of self-contained non-volatile memory elements. The settings of the memory elements are determined by repeatedly testing the possible values until an optimal one is chosen. The testing process is accelerated by eliminating the need to re-write the non-volatile memory for each value that is tested.
Claims11
A system for compensating the response of an analog integrated circuit comprising:
- a non-volatile memory;
- a data register;
- a control register;
- a compensator generating an adjustment signal;
- a multiplexer;
- wherein the control input of said multiplexer is coupled to said control register, a first data input of said multiplexer is coupled to said non-volatile memory, a second data input of said multiplexer is coupled to said data register, and the output of said multiplexer is coupled to the input of said compensator;
- one or more test buses for controlling the contents of said non-volatile memory, said control register and said data register;
- and
- an analog circuit connected to said adjustment signal, wherein the response of said analog circuit is adjusted by said adjustment signal.
6 more elements
A method of setting a compensation circuit for an analog circuit comprising the steps of:
- placing said compensation circuit in a test mode;
- setting a volatile register to one of a plurality of compensation values;
- measuring the response of said analog circuit;
- repeating said setting step and said measuring step with different compensation values;
- selecting one compensation value;
- and
- programming a non-volatile memory to said one compensation value.
4 more elements
Dependencies are inferred from the claim text.