Direct bit line-bit line defect detection test mode for SRAM

A method for testing a semiconductor memory device, said method comprising:

• coupling a first common line within the memory device to a first set of bit lines within the memory device only when a test signal is active;
• coupling a second common line within the memory device to a second set of bit lines within the memory device only when a test signal is active;
• and
• measuring a resistance between the first and second common lines.

A semiconductor memory device, comprising:

• an array of bit lines comprising interleaved first and second sets of bit lines, such that one bit line from the second set is interposed between any two adjacent bit lines from the first set;
• a first common line coupled to all of the bit lines within the first set;
• a second common line coupled to all of the bit lines within the second set;
• and
• a plurality of switches, wherein a first set of the switches is adapted to electrically connect each bit line of the first set of bit lines to the first common line only when a test signal is active, and wherein a second set of the switches is adapted to electrically connect each bit line of the second set of bit lines to the second common line only when the test signal is active.