Integrated circuit having forced substrate test mode with improved substrate isolation

An integrated circuit memory device comprising:

• an array of memory cells;
• a substrate;
• an external connection for receiving an input signal from an external source;
• and
• an isolation circuit coupled between the external connection and the substrate to electrically isolate the external connection from the substrate during non-test operations to isolate from the substrate all input signal voltages applied to the external connection, including input signal voltages having a voltage which is less than an n-channel threshold voltage below a substrate voltage.

An integrated circuit comprising:

• an external connection for receiving an input signal;
• and
• an isolation circuit coupled between the external connection and a substrate of the integrated circuit comprising:
• a first n-channel transistor having a drain coupled to the external connection, and a source coupled to the substrate,
• a second n-channel transistor having a drain coupled to the external connection, a source coupled to a gate of the first n-channel transistor, and a gate coupled to receive a control signal that is low during a test mode, and
• a p-channel transistor having a drain coupled to receive an inverse of the control signal, a source coupled to the gate of the first n-channel transistor, and a gate coupled to the gate of the second n-channel transistor.

An integrated circuit comprising:

• an external connection for receiving an input signal;
• and
• an isolation circuit coupled between the external connection and a substrate of the integrated circuit comprising:
• a p-channel transistor having a source coupled to the external connection, a drain coupled to the substrate, and a gate coupled to receive a control signal that is low during a test mode;
• and
• an n-channel transistor having a drain connected to the gate of the p-channel transistor, a source connected to a resistor, and a gate connected to receive an inverse of the control signal, the resistor is connected between the source of the n-channel transistor and the external connection.

An integrated circuit memory device comprising:

• an array of memory cells;
• a substrate;
• an external connection for receiving an input signal;
• and
• an isolation circuit coupled between the external connection and the substrate comprising:
• a first n-channel transistor having a drain coupled to the external connection, and a source coupled to the substrate,
• a second n-channel transistor having a drain coupled to the external connection, a source coupled to a gate of the first n-channel transistor, and a gate coupled to receive a control signal that is low during a test mode, and
• a p-channel transistor having a drain coupled to receive an inverse of the control signal, a source coupled to the gate of the first n-channel transistor, and a gate coupled to the gate of the second n-channel transistor.

An integrated circuit memory device comprising:

• an array of memory cells;
• a substrate;
• an external connection for receiving an input signal;
• and
• an isolation circuit coupled between the external connection and the substrate comprising:
• a p-channel transistor having a source coupled to the external connection, a drain coupled to the substrate, and a gate coupled to receive a control signal that is low during a test mode;
• and
• an n-channel transistor having a drain connected to the gate of the p-channel transistor, a source connected to a resistor, and a gate connected to receive an inverse of the control signal, the resistor is connected between the source of the n-channel transistor and the external connection.

A method of operating in integrated circuit memory device having a substrate, the method comprising:

• during a test mode operation, activating a p-channel transistor coupled between the substrate and an external connection, and activating an n-channel transistor coupled between the external connection via a resistor, and a gate of the p-channel transistor;
• providing a voltage on the external input connection to establish a substrate voltage during the test mode operation;
• and
• deactivating the p-channel and n-channel transistors during non-test mode operation.

A method of operating in integrated circuit memory device having a substrate, the method comprising:

• during a test mode operation, activating a first n-channel transistor coupled between an external connection and the substrate, and turning off a second n-channel transistor coupled between a gate of the first n-channel transistor and the external connection;
• providing a voltage on the external input connection to establish a substrate voltage during the test mode operation;
• and
• during a non-test mode operation, turning off the first n-channel transistor, and activating the second n-channel transistor.