Nonvolatile semiconductor memory device with improved reliability and operation speed
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYasuhiro Yamamoto, Tomoshi Futatsuya, Yoshikazu Miyawaki
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Abstract
A memory transistor for a lock bit, holding information on whether a memory block can be erased/reprogrammed, is provided in the same column as that of a plurality of dummy cells. Since a sub bit line for reading the lock bit is electrically isolated from a sub bit line for dummy cell, accurate lock-bit reading is possible even when the dummy cell is over erased. Thus, a nonvolatile semiconductor memory device advantageous in reliability and operation time can be provided.
Claims17
A nonvolatile semiconductor memory device comprising memory blocks each as a unit for collectively performing an erasing operation,
- each of said memory blocks including
- a plurality of normal memory cells arranged in matrix of normal rows and normal columns, holding normal data provided from an external source, and
- a lock-bit cell column provided adjacent to at least any one of said normal columns, holding a lock bit forming permission information on programming and erasing for said memory blocks;
- and
- said lock-bit cell column including
- a first field effect transistor connected between a first internal node and a second internal node, having a first floating gate and holding said lock bit depending on a threshold voltage, and
- a second field effect transistor having a second floating gate and connected between said second internal node and a third internal node electrically isolated from said first internal node.
A nonvolatile semiconductor memory device comprising memory blocks each as a unit for collectively performing an erasing operation,
- each of said memory blocks including
- a plurality of normal memory cells arranged in matrix of normal rows and normal columns, holding normal data provided from an external source,
- a plurality of word lines respectively provided corresponding to said normal rows, and
- a lock-bit cell column provided adjacent to at least any one of said normal columns, holding a lock bit forming permission information on programming and erasing for said memory blocks;
- said lock-bit cell column including first and second field effect transistors each having a control gate and a floating gate;
- said first field effect transistor being connected between a first internal node and a second internal node and holding said lock bit depending on a threshold voltage, the control gate thereof being connected to any one of said plurality of word lines;
- and
- said second field effect transistor being connected in parallel with said first field effect transistor, the control gate thereof being connected to a third internal node having a potential which causes no extraction of electrons from said floating gate at the time of collective erasing of each of said memory blocks.
A nonvolatile semiconductor memory device comprising memory blocks each as a unit for collectively performing an erasing operation;
- each of said memory blocks including
- a plurality of normal memory cells arranged in matrix of normal rows and normal columns, holding normal data provided from an external source, and
- a lock-bit cell column provided adjacent to at least any one of said normal columns, holding a lock bit forming permission information on programming and erasing for said memory blocks;
- and
- said lock-bit cell column including
- a first field effect transistor connected between a first internal node and a second internal node, having a floating gate and holding said lock bit depending on a threshold voltage, and
- a second field effect transistor without floating gate, connected in parallel with said first field effect transistor.
A nonvolatile semiconductor memory device, comprising:
- a plurality of first memory cells arranged in a matrix of a plurality of first columns and a plurality of first rows, holding data provided from an external source;
- a plurality of first bit lines provided respectively corresponding to said plurality of first columns;
- a second column provided adjacent to at least one of said plurality of first columns;
- and
- a second bit line provided corresponding to said second column,
- said second column including
- a second memory cell holding data provided from an external source, and
- a third memory cell set to be in a non-programmable state for data provided from an external source.
A nonvolatile semiconductor memory device, comprising memory blocks each of said memory blocks including
- a plurality of first memory cells arranged in a matrix of a plurality of first columns and a plurality of first rows, holding data provided from an external course,
- a second column provided adjacent to at least one of said plurality of first columns, and
- a second bit line provided corresponding to said second column,
- said second column including
- a second memory cell holding a lock bit provided from an external source, the lock bit forming permission information on programming and erasing for a corresponding one of said memory blocks, and
- a third memory cell set to be in a non-programmable state for data provided from an external source.
Dependencies are inferred from the claim text.