Semiconductor memory device having faulty cells

A storage device comprising:

• a system interface unit which carries out interface with a host system via an external bus;
• a controller coupled with said system interface unit which analyzes commands received by said system interface unit from said host system and controls operations to be performed within said storage device;
• a non-volatile semiconductor memory coupled with said controller;
• a non-volatile semiconductor memory coupled with said controller;
• an error correction unit, coupled with said non-volatile semiconductor memory, which performs an error detection and an error correction operation for data stored in said non-volatile semiconductor memory;
• and
• two memories coupled between said system interface unit and said non-volatile semiconductor memory,
• wherein said non-volatile semiconductor memory is electrically erasable and electrically programmable and stores data from said host system via said system interface unit, and
• wherein, in response to a read command received by said system interface unit, said controller carries out a read operation of data to said two memories from said non-volatile semiconductor memory to carry out parallel operations of data transferring of data which has been subjected to the error detection and error correction operation by said error correction unit from one of said two memories to said host system via said system interface unit and of data transferring of subsequent data which is to be subjected to the error detection and error correction operation from said non-volatile semiconductor memory to another of said two memories.

A storage device comprising:

• a system interface unit which carries out interface with a host system via an external bus;
• a controller coupled with said system interface unit which analyzes commands received by said system interface unit from said host system and controls operations to be performed within said storage device;
• a non-volatile semiconductor memory coupled with said controller;
• an error correction unit, coupled with said non-volatile semiconductor memory, which performs an error detection and error correction operation for data stored in said non-volatile semiconductor memory;
• and
• two memories coupled between said system interface unit and said non-volatile semiconductor memory,
• wherein said non-volatile semiconductor memory is electrically erasable and electrically programmable and stores data from said host system via said system interface unit, and
• wherein, in response to a read command received by said system interface unit, said controller carries out a read operation of data to said two memories from said non-volatile semiconductor memory to carry out overlap operations of data transferring of data which has been subjected to the error detection and error correction operation by said error correction unit from one of said two memories to said host system via said system interface unit and of data transferring of subsequent data which is to be subjected to the error detection and error correction operation from said non-volatile semiconductor memory to another of said two memories.