Transistor protecting circuit with enhancing circuit for H bridge circuit

A transistor protecting circuit for an H bridge circuit in which a first P-channel transistor having a first gate and a first N-channel transistor having a second gate are provided in series between a first power supply and a ground through a first node provided between said first P-channel transistor and said first N-channel transistor, and a second P-channel transistor and a second N-channel transistor are provided in series between the first power supply and the ground through a second node provided between said second P-channel transistor and said second N-channel transistor, a load being connected between said first node and said second node, said transistor protecting circuit comprising:

• a first buffer inverting a first control signal to a first gate signal which is supplied to said first gate of said first P-channel transistor via a first line;
• a second buffer inverting a second control signal to a second gate signal which is supplied to said second gate of said first N-channel transistor via a second line;
• and
• an enhancing circuit connected to said first gate and second gate via said first line and said second line, respectively;
• wherein said enhancing circuit supplies first current to said first gate via said first line when said first N-channel transistor is turned on in response to said second gate signal while said first P-channel transistor is in an off state in response to said first gate signal, and supplies second current to said ground via said second line when said first P-channel transistor is turned on in response to said first gate signal while said first N-channel transistor is in an off state in response to said second gate signal.