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US 6,388,672 B1Granted
Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit
AssigneeKabushiki Kaisha Toshiba
InventorsNobuhiro Ide, Atsushi Kunimatsu, Maki Ueno
Life of this patent
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Abstract
An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.
Claims9
A graphic translate engine for performing a predetermined geometrical arithmetic processing with respect to vertex data of a figure stored to an external memory unit, the graphic translate engine comprising:
- an internal memory section divided into first and second memory blocks and capable of inputting and outputting data every memory block;
- a data holding section for temporarily storing one portion of said vertex data stored in said internal memory section;
- and
- an arithmetic section for receiving the vertex data stored in the data holding section and generating graphic data by performing predetermined processing of the vertex data, and outputting the graphic data to said data holding section;
- wherein during a period of time, the first memory block of said internal memory section is connected to said external memory unit and the second memory block thereof is connected to said data holding section and the first memory block outputs the graphic data to said external memory unit and then receives the vertex data from said external memory unit while the second memory block outputs the vertex data to said data holding section and then receives the graphic data from said data holding section,
- wherein, during a succeeding period of time, the first memory block is connected to said data holding section and the second memory block is connected to said external memory unit and the second memory block outputs the graphic data to said external memory unit and then receives the vertex data from said external memory unit while the first memory block outputs the vertex data to said data holding section and then receives the graphic data from said data holding section, and
- wherein the alternative connection is repeated.
4 more elements
A graphic translate engine comprising:
- multiply-add calculation units for making a multiply-accumulation operation of x, y and z corresponding to x, y and z;
- at least one divider;
- first, second and third register files for storing vertex data of a figure corresponding to x, y and z;
- a first bus network for connecting each first reading port of said first, second and third register files with a corresponding input terminal for a first operand of said multiply-add calculation units and said divider, and supplying first operand data to said multiply-add calculation units and said divider;
- a second bus network for connecting, by a crossbar switch included therein, each second reading port of said first, second and third register files with each input terminal for a second operand of said multiply-add calculation units and said divider in a one-to-one corresponding manner in which each register file is exclusively connected to any one of said multiply-add calculation units and said divider or in a one-to-multiple corresponding manner in which one of said first, second and third register files is connected to two or more than two of said multiply-add calculation units and said divider, and for supplying second operand data to said multiply-add calculation units and said divider;
- and
- a third bus network for exclusively connecting each writing port of said first, second and third register files with any output terminal of said multiply-add calculation units and said divider, and writing back calculation results of said multiply-add calculation units and said divider to a predetermined address of said first, second and third register files.
4 more elements
A graphic translate engine comprising:
- multiply-add calculation units for making multiply-accumulation operation of x, y, z and w corresponding to x, y, z and w;
- at least one divider;
- first, second, third and fourth register files for storing vertex data of a figure corresponding to x, y, z and w;
- a first bus network for connecting each first reading port of said first, second, third and fourth register files with a corresponding input terminal for a first operand of said multiply-add calculation units and said divider, and supplying first operand data to said multiply-add calculation units and said divider;
- a second bus network for connecting, by a crossbar switch included therein, each second reading port of said first, second, third and fourth register files with each input terminal for a second operand of said multiply-add calculation units and said divider in a one-to-one corresponding manner in which each register file is exclusively connected to any one of said multiply-add calculation units and said divider or in a one-to-multiple corresponding manner in which one of said first, second, third and fourth register files is connected to two or more than two of said multiply-add calculation units and said divider, and for supplying second operand data to said multiply-add calculation units and said divider;
- and
- a third bus network for exclusively connecting each writing port of said first, second, third and fourth register files with any output terminal of said multiply-add calculation units and said divider, and writing back calculation results of said multiply-add calculation units and said divider to a predetermined address of said first, second, third and fourth register files.
4 more elements
A floating point multiply-add calculation unit for receiving first, second and third operands and calculating a multiply-add of these operands, the floating point multiply-add calculation unit comprising:
- a multiplying section that calculates a product of said first and second operands;
- a digit-aligning section that receives a shifting mount as information for a digit alignment and that digit-aligns said third operand or a preceding multiply-add calculation result with the product of said first and second operands according to the shift amount, said digit-aligning section digit-aligning said third operation upon a first multiply-add calculation and digit-aligning the preceding multiply-add calculation result upon second and succeeding multiply-add calculations;
- an adding section that calculates a sum of the product of said first and second operands and the digit-aligned third operand or the digit-aligned preceding multiply-add calculation result;
- a normalizing section that normalizes a mantissa of a multiply-add calculation result obtained through said adding section;
- an exponent part arithmetic section that calculates an exponent of the product of said first and second operands;
- a shifting amount calculating section that calculates a difference between the exponent of the product of the first and second operands and an exponent part of said third operand or an exponent part of the preceding multiply-add calculation as said shifting amount and that outputs said shifting amount to said digit-aligning section;
- and
- an exponent part normalizing arithmetic section that normalizes the exponent part of said preceding multiply-add calculation.
5 more elements
Dependencies are inferred from the claim text.