Low voltage control method for a ferroelectric liquid crystal matrix display panel

A method for controlling a matrix display panel in which each picture element (pixel) ideally corresponds to an intersection of an element of a first electrode assembly and an element of a second electrode assembly and to an electro-optical, multistable cell comprising a ferroelectric liquid crystal existing between two facing electrodes belonging to said two electrode assemblies, said multistable cell having as a characteristic parameter, a minimum product time x voltage, Amin, within a voltage range of interest, when spaced apart rectangular pulses having alternately opposite polarities are applied, adapted to switch said cell from an extreme state to another state, when between pulses a voltage of constant r.m.s. amplitude Vhf is applied, in which method selection voltages are applied to electrodes of said first assembly and each of these voltages is associated, at each selection operation of said panel, to a control time window not overlapping to other control time windows for all cells corresponding to said electrode of said first assembly, while data voltages are applied to electrodes belonging to said second electrode assembly and each of these data voltages is formed by superposing a data voltage for each pixel, namely voltages applied within different time windows associated with selection voltages and designed to control each of said cells corresponding to said electrode belonging to said second electrode assembly, said voltages depending on each value describing a pixel of an image to be displayed in correspondence to said electrode of said second assembly, wherein in a basic representation obtained by assuming, as a voltage ideal reference, a one for which a central value of an envelope of data voltages is constant and each data voltage has a null average value, independently from a position of a corresponding pixel and from a value describing it, said average value of each selection voltage, calculated both globally and within each control window associated with other selection windows and not overlapping with selection time, namely a time between a first pulse and an end of a last pulse relating to a selection operation, in said selection voltage, is substantially null,

• characterized in that selection voltages include various successive portions which have a duration longer than a time control window, substantially corresponding to a single polarity and having an average voltage in a range of 0.95 times Vs+ to 0.95 times Vs−, where Vs+ and Vs− are positive and negative peak values in said selection voltage assembly and said selection voltage assembly has overlapping selection times and is such that all positive voltages higher than 0.9 times said positive peak values Vs+ are included in a first time interval set and all negative voltages higher in absolute value than 0.9 times said negative peak values Vs− are included in a second time interval set, time intervals of said second set being interlaced without overlaps with time intervals voltages of said first set, with intervals of both sets within each time control window substantially corresponding to two polarities of said selection voltage associated with a concerned window;
• and in that the integrated circuits that generate said selection voltages are supplied with undulated voltages which, with respect to an ideal reference, have maximum values in time intervals of said first set and minimum values in time intervals of said second set and have peak-to-peak amplitudes higher than 0.1 times the difference between said values of said positive peaks Vs+ and of said negative peaks Vs−.