Apparatus and method for receiving data serially for use with an advanced technology attachment packet interface (atapi)

A receiver interface for interfacing with an Advanced Technology Attachment Packet Interface (ATAPI) in a first device, the receiver interface comprising:

• a. a converter converting a first set of signals from a serial bus into a second set of signals, the first set of signals being serial to one another and using low-voltage, differential signaling (LVDS), the first set of signals being adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) Bus, the second set of signals being serial to another, using TTL voltage levels, and single-ended signaling, the second set of signals using a packet format to represent a packet;
• b. a depacketizing circuit disassembling the packet represented by the second set of signals to generate a third set of signals, the third set of signals being parallel to one another and using TTL, single-ended signaling, the third set of signals representing a payload of the packet;
• and
• c. an ATAPI receiver circuit for storing a fourth set of signals at a location within the ATAPI in response to the third set of signals, the fourth set of signals representing a portion of the payload of the packet;
• wherein the converter supports a transfer rate at least twice that of the IDE bus.

A method of interfacing between a serial bus and a first device including an Advanced Technology Attachment Packet Interface (ATAPI), the method comprising:

• a. receiving a first set of signals from the serial bus, the first set of signals being serial to one another and using low-voltage, differential signaling (LVDS), the first set of signals being received at a transfer rate that can be increased without increasing a number of lines of the serial bus;
• b. generating a second set of signals from the first set of signals, the second set of signals representing a packet, the second set of signals being parallel to one another and using Transistor-Transistor Logic (TTL) voltage levels, single-ended signaling;
• c. disassembling the packet represented by the second set of signals to generate a third set of signals, the third set of signals representing a payload of the packet, the third set of signals being parallel to one another and using TTL voltage levels, single-ended signaling;
• d. determining a payload type using the third set of signals and generating a fourth set of signals to represent the payload type;
• e. addressing a first register of a task file of the ATAPI using the fourth set of signals;
• and
• f. coupling a fifth set of signals to the first register of the task file, the fifth set of signals representing a portion of the payload, the fifth set of signals being parallel to one another and using TTL voltage level, single-ended signaling.

A receiver interface for interfacing with an Advanced Technology Attachment Packet Interface (ATAPI) in a first device, the receiver interface comprising:

• a converter converting a first serial, packetized set of signals received from a bus into a second parallel set of signals;
• and
• an ATAPI receiver circuit for transferring the second parallel set of signals to the ATAPI;
• wherein the first serial, packetized set of signals are adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) Bus.

A receiver interface in a first device, the receiver interface comprising:

• a serial interface to a bus;
• a parallel interface to an Advanced Technology Attachment Packet Interface (ATAPI);
• and
• a converter which converts a first set of serial signals received from the serial interface to the bus into a second set of parallel signals to be transmitted over the parallel interface to the ATAPI.