Method and circuit for codes generation
AssigneeYozan Inc.
InventorsBiqi Long, Changming Zhou
Life of this patent
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Abstract
The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.
Claims6
A method for code generation wherein the method involves
- setting of a vector comprising bit strings of a plurality of bits;
- addition of a plurality of combinations of bits in said vector taking 2 as a modulus;
- input of each added result to a predetermined bit position;
- circular-shift of said vector;
- and output of the bit at said predetermined bit position, in generating a long-code of a mobile station set a long-code cycle in synchronization with that of a base station, the method further comprising the steps of:
- dividing one cycle in said long-code cycle of said mobile station into a plurality of sub-cycles;
- setting a combination of said sub-cycles, to express a time taking said sub-cycles as unit;
- previously generating mask data comprising a bit string corresponding to a number of cyclic shifts corresponding respectively to a period of a combination of said sub-cycles;
- when generation of said long codes is required, selecting a pre-set timing at timing taking said sub cycle as a unit in the proximity of immediately after the generation of said long codes is required;
- selecting said mask data corresponding to a period between said pre-set timing and the beginning of the long-code cycle including said pre-set timing;
- and
- starting said long-code generation from said pre-set timing, using a vector generated by sequential operation of said mask data and an initial value of said vector.
A circuit for code generation, said circuit comprising:
- a shift register of a first-stage storing an initial value of a vector;
- a mask of multi-stages, each corresponding to respective mask data, storing the corresponding mask data, performing logical products and further exclusive-OR operations with input vectors;
- a shift register of multi-stages provided to correspond to said masks storing outputs of masks at each stage;
- a first multiplexer of the multi-stages outputting each bit of said shift register of the first-stage, or selectively that of said shift register of the first-stage to a mask of a second-stage, and a first multiplexer subsequent to the second-stage outputting each bit of said shift register subsequent to the second-stage, or selectively that of a shift register of a previous-stage to a mask subsequent to a third mask;
- and
- a second multiplexer selectively outputting any one of the outputs of said first-stage shift register, and the output of each mask.
Dependencies are inferred from the claim text.