US 6,388,546 B1Granted

Method and apparatus for cascading frequency doublers

AssigneesHer Majesty the Queen in right of Canada, as represented by the Minister of Industry through the Communications Research Centre, The Communications Research Laboratory of the Ministry of Posts and Telecommunications, Japan

InventorsMasahiro Kikokawa, Malcolm G. Stubbs

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Abstract

This invention provides a multistage frequency multiplier having a plurality of frequency doublers. Each doubler incorporates a three-terminal transistor device and is connected to an adjacent doubler via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubler. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubler. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator. This invention is particularly useful in high-speed, large-capacity communications systems and in microwave and millimeter-wave radar applications.

Claims18

Dependent claims

A method of frequency multiplication comprising the steps of:

(a) receiving an input signal having a fundamental frequency of component f0;
(b) providing an input impedance matching to said fundamental frequency component;
(c) performing a plurality of n frequency doubling operations in series to derive from the input signal an output signal having an output frequency component of 2nf0,
wherein each frequency doubling operation, hereby referred to as a k′ th doubling operation k≲n, includes the steps of
receiving a k′ th input signal having an input frequency component of 2(k-1)f0,
deriving from the k′ th input signal a k′ th intermediate signal having a harmonic frequency component of 2kf0,
suppressing the input frequency component of 2(k-1)f0 from the intermediate signal;
and
(d) providing an interstage impedance matching to the harmonic frequency component of 2kf0 between each pair of consecutive k′ th and (k+1)′ th frequency doubling operations;
the interstage impedance matching being provided by a transmission line having electrical parameters so set as to provide a pair of reflection coefficients on the transmission line having phases of similar values and opposite polarities, when seen in opposite directions to one another at the harmonic frequency component of 2kf0;
and
(e) providing an output impedance matching to the output frequency component of 2nf0.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/390,576Filed 3 Sep 1999
Priority: CA 22445074 Sep 1998
Granted: 14 May 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03B 19/14
By means of discharge device or semiconductor device with more than two electrodes: by means of a semiconductor device
H01P 5/02
Coupling devices of the waveguide type: with invariable factor of coupling
H03B 19/18
Using uncontrolled rectifying devices, e.g. rectifying diodes or Schottky diodes: and elements comprising distributed inductance and capacitance
H03B
Generation of oscillations, directly or by frequency-changing, by circuits employing active elements