Integrated circuit generating a voltage linear ramp having a low raise

A device for controlling the slew ate of a current supplied by a power transistor having at least one control terminal and two main conduction terminals and comprising:

• a circuit input terminal coupled to a first voltage reference;
• a circuit output terminal for providing a controlled ramp signal;
• an operational amplifier having a non-inverting input terminal connected to the circuit input terminal, and having an inverting input terminal coupled to the circuit output terminal;
• a storage capacitor connected between the non-inverting input terminal of the operational amplifier and a second voltage reference, and structured to be charged by a pumping capacitor coupled between the non-inverting input terminal and the output terminal;
• and
• first and second active passgates having respective drive terminals connected to each other and to a first control terminal of the ramp generator circuit and structured to receive a first clock signal.

A battery-charger/battery system, in particular for use with cellular telephony, comprising a device for controlling the slew rate of a current supplied by a power transistor coupled between the battery-charger and the battery, comprising:

• a circuit input terminal coupled to a first voltage reference;
• a circuit output terminal for providing a controlled ramp signal,
• an operation amplifier having a non-inverting input terminal connected to the circuit input terminal, and having an inverting input terminal coupled to the circuit output terminal;
• a storage capacitor connected between the non-inverting input terminal of the operational amplifier and a second voltage reference, and structured to be charged by a pumping capacitor coupled between the non-inverting input terminal and the output terminal;
• and
• first and second active passgates having respective drive terminals connected to each other and to a first control terminal of the ramp generator circuit and structured to receive a first clock signal.

A method of generating a positive ramp voltage signal and a negative ramp voltage signal, comprising:

• controlling a first pair of passgates with a first clock signal;
• when the first pair of passgates is in a first state, charging a first capacitor from a voltage reference;
• controlling a second pair of passgates with a second clock signal;
• when the second pair of passgates is in the first state, sharing the charge stored in the first capacitor between the first capacitor and a second capacitor coupled in parallel to the first capacitor;
• controlling a third pair of passgates by a third clock signal;
• and
• when the third pair of passgates is in a first state, discharging a portion of the charge stored in the second capacitor to hereby generate the negative ramp voltage signal.

An integrated voltage ramp generator circuit comprising:

• first and second passgates activated by a first signal;
• a first capacitance switchably coupled by the first and second passgates, respectively, between a first reference voltage at a first terminal of the first capacitance and a second reference voltage at a second terminal of the first capacitance;
• third and fourth passgates activated by a second signal;
• a second capacitance switchably coupled by the third and fourth passgates, respectively, to the first capacitance at a first terminal of the second capacitance;
• and the second capacitance coupled to the second reference voltage at a second terminal of the second capacitance;
• and
• a differential amplifier having a non-inverting input coupled to the first terminal of the second capacitance, having an inverting input switchably coupled by the second signal to the second terminal of the first capacitance, and the inverting input coupled to an output of the differential amplifier.

A ramp voltage generating circuit, comprising

• an input terminal for accepting a first reference voltage;
• a first switching structure coupled between the input terminal and a first terminal of a first capacitor;
• a second switching structure coupled between a second terminal of the first capacitor and a second voltage reference;
• a third switching structure coupled between a first terminal of the first capacitor and a first terminal of a second capacitor;
• an operational amplifier having an input coupled to the first terminal of the second capacitor, and having an output terminal;
• and
• a fourth switching structure coupled between a second terminal of the operational amplifier and the second terminal of the first capacitor.