Semiconductor output circuit

A semiconductor output circuit comprising:

• a first power source line;
• a second power source line having a lower voltage than said first power source line;
• an intermediate power source line having a voltage lower than that of said first power source line and higher than that of said second power source line;
• an output node of an NPN transistor to which a collector of said NPN transistor and one of the terminals of a load circuit are connected;
• a circuit comprised of an active element or an impedance element having one of its terminals connected to said output node,
• a protective diode configured to protect said NPN transistor,
• wherein said circuit comprised of the active element or the impedance element causes a reverse operation of said NPN transistor reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, and said protective diode protects said NPN transistor from said reverse operation, and
• wherein an emitter of said NPN transistor is connected to said intermediate power source line, the other terminal of said load circuit is connected to said first power source line, the other terminal of said circuit comprised of the active element or the impedance element is connected to said second power source line, a cathode of said protective diode is connected to the collector of said NPN transistor, and an anode of said protective diode is connected to a base of said NPN transistor.

A semiconductor output circuit comprising:

• a first power source line;
• a second power source line having a lower voltage than said first power source line;
• an intermediate power source line having a voltage lower than that of said first power source line and higher than that of said second power source line;
• an output node of an PNP transistor to which a collector of said PNP transistor and one of the terminals of a load circuit are connected;
• an a circuit comprised of an active element or an impedance element having one of its terminals connected to said output node, and
• a protective diode configured to protect said PNP transistor,
• wherein said circuit comprised of the active element or the impedance element causes a reverse operation of said PNP transistor reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, and said protective diode protects said PNP transistor from said reverse operation, and
• wherein an emitter of said PNP transistor is connected to said intermediate power source line, the other terminal of said load circuit is connected to said second power source line, the other terminal of said circuit comprised of the active element or the impedance element is connected to said first power source line, a cathode of said protective diode is connected to a base of said PNP transistor, and an anode of said protective diode is connected to the collector of said PNP transistor.