Dynamic termination and clamping circuit
AssigneeSun Microsystems, Inc.
InventorsAninda Roy, Gajendra P. Singh
Life of this patent
Estimating the term…
Abstract
The present invention is directed to an apparatus and method to clamp and terminate signals along a communication bus; the clamping and termination are performed dynamically whenever a signal exceeds a set peak value or falls below a set low value. Variations include a clamping and termination circuit made of metal oxide semiconductor (MOS) devices where one MOS device clamps for over-voltage and another MOS device clamps for under-voltage. Biasing circuits to the gates of the MOS devices assure that proper bias voltage is applied so that the MOS devices only clamp and terminate when a signal is received and that signal falls off the set high or low values, this assures dynamic clamping and termination and avoids unnecessary additional voltage from a driving device.
Claims12
An active clamping and terminating circuit in a communication system connected to a bus comprising:
- a first MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the drain of the first MOS transistor is connected to the bus;
- a second MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the source of the second MOS transistor is connected to the bus;
- a first circuit stage providing a bias voltage of VTN to the gate of the first MOS transistor comprised of
- a third MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the drain of the third MOS transistor is connected to the gate of the first MOS transistor, the source of the third MOS transistor is connected to VDD;
- a fourth MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the gate and the source of the fourth MOS transistor is connected to the gate of the third MOS transistor;
- a fifth MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the gate and the source of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the drain of the fifth MOS transistor is connected to ground;
- a first resistor with one end connected to the source of the fourth MOS transistor, the other end connected to VDD, and
- a second resistor with one end connected to ground and the other end connected to the drain of the third MOS transistor and the gate of the first MOS transistor;
- and
- a second circuit stage providing a bias voltage of VDD−VTP to the gate of the second MOS transistor
- wherein the first MOS transistor clamps and terminates voltage when voltage along the bus falls below VSS, and the second MOS transistor clamps and terminates voltage when voltage along the bus exceeds VDD.
An active clamping and terminating circuit in a communication system connected to a bus comprising:
- a first MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the drain of the first MOS transistor is connected to the bus;
- a second MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the source of the second MOS transistor is connected to the bus;
- a first circuit stage providing a bias voltage of VTN to the gate of the first MOS transistor;
- and
- a second circuit stage providing a bias voltage of VDD−VTP to the gate of the second MOS transistor comprised of
- a sixth MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the source of the sixth MOS transistor is connected to the gate of the second MOS transistor, the drain of the third MOS transistor is connected to ground;
- a seventh MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the gate and the drain of the seventh MOS transistor is connected to the gate of the sixth MOS transistor;
- an eighth MOS transistor comprised of
- a source,
- a drain, and
- a gate, whereby the gate and the drain of the eighth MOS transistor is connected to the source of the seventh MOS transistor, the source of the eighth MOS transistor is connected to VDD;
- a third resistor with one end connected to the drain of the seventh MOS transistor, the other end connected to ground, and
- a fourth resistor with one end connected to VDD and the other end connected to the source of the sixth MOS transistor and the gate of the second MOS transistor;
- wherein the first MOS transistor clamps and terminates voltage when voltage along the bus falls below VSS, and the second MOS transistor clamps and terminates voltage when voltage along the bus exceeds VDD.
Dependencies are inferred from the claim text.