Clock period sensing circuit

An interpolator comprising:

• first, second and third timing dividing circuits connected in parallel and each having a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input, and first and second N-type transistors, which are driven by a constant-current source, connected between said internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs;
• a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
• each timing dividing circuit having an inverter for inverting and outputting a potential present at said internal node;
• wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to said first timing dividing circuit;
• first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to said second timing dividing circuit;
• a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to said third timing dividing circuit;
• and
• a clock period sensing circuit comprising:
• a plurality of delay circuits to which a clock signal is applied as a common input and which are arranged in parallel and have delay times that differ from one another;
• a plurality of latch circuits to which outputs of respective ones of said delay circuits are input for latching the clock signal as a latch timing signal;
• and
• a plurality of encoder circuits to which the outputs of said latch circuits are input for encoding information representing a boundary between delay circuits traversed by the clock signal and delay circuits not traversed by the clock signal, and outputting the encoded information as a control signal;
• the capacitance of said interpolator being selected by the control signal from the clock period sensing circuit.

An interpolator comprising:

• first, second and third timing dividing circuits connected in parallel and each having a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input, and first and second N-type transistors, which are driven by a constant-current source, connected between said internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs;
• a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
• each timing dividing circuit having an inverter for inverting and outputting a potential present at said internal node;
• wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to said first timing dividing circuit;
• first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to said second timing dividing circuit;
• a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to said third timing dividing circuit;
• and
• a clock period sensing circuit comprising:
• a plurality of delay circuits to which a clock signal is applied as a common input and which are arranged in parallel and have delay times that differ from one another;
• a plurality of latch circuits to which outputs of respective ones of said delay circuits are input for latching the clock signal as a latch timing signal;
• and
• a plurality of encoder circuits to which the outputs of said latch circuits are input for encoding information representing a boundary between delay circuits traversed by the clock signal and delay circuits not traversed by the clock signal, and outputting the encoded information as a control signal, and
• wherein said plurality of delay circuits have operating ranges that overlap each other slightly and centers of operation that differ from one another, and
• the capacitance of said interpolator being selected by the control signal from said clock period sensing circuit.

An interpolator comprising:

• first, second and third timing dividing circuits connected in parallel and each having a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input, and first and second N-type transistors, which are driven by a constant-current source, connected between said internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs;
• a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
• each timing dividing circuit having an inverter for inverting and outputting a potential present at said internal node;
• wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to said first timing dividing circuit;
• first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to said second timing dividing circuit;
• a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to said third timing dividing circuit;
• and
• a clock period sensing circuit comprising:
• a plurality of delay circuits to which a clock signal is applied as a common input and which are arranged in parallel and have delay times that differ from one another;
• a plurality of latch circuits to which outputs of respective ones of said delay circuits are input for latching the clock signal as a latch timing signal;
• and
• a plurality of encoder circuits to which the outputs of said latch circuits are input for encoding information representing a boundary between delay circuits traversed by the clock signal and delay circuits not traversed by the clock signal, and outputting the encoded information as a control signal, and
• wherein each of said delay circuits has:
• a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by inverting an input signal is applied as a gate input;
• and
• an N-type transistor, which is driven by a constant-current source, connected between said internal node and ground and to which the signal obtained by inverting the input signal is applied as a gate input;
• a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
• said delay circuit having an inverter for inverting and outputting a potential present at said internal node;
• the capacitance of said interpolator being selected by the control signal from said clock period sensing circuit.

An interpolator comprising:

• first, second and third timing dividing circuits connected in parallel and each having a first-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking logic between first and second input signals is applied as a gate input, and first and second-type transistors, which are driven by a constant-current source, connected between said internal node and ground and to which a signal obtained by inverting said signal obtained from the first and second input signals is applied as gate inputs;
• a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
• each timing dividing circuit outputting an output signal indicative of a potential present at said internal node;
• wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to said first timing dividing circuit;
• first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to said second timing dividing circuit;
• a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to said third timing dividing circuit, and
• a clock period sensing circuit comprising:
• a plurality of parallel connected delay sensing circuits having slightly overlapping operating ranges and different centers of operation,
• wherein a clock signal is passed through said plurality of delay sensing circuits, and a period of the clock is sensed using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed,
• the capacitance of said interpolator being selected by the control signal from said clock period sensing circuit.