Large input function replaying dynamic entry latch with static and monotonic dual rail outputs

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• a signal path and a pull-down stack with a first FET between the signal path and ground;
• a second FET between a source voltage and the signal path, wherein the second FET is driven by the at least one clock waveform input signal;
• and
• a third FET between the voltage source and the first dynamic signal output and a fourth FET between the first dynamic signal output and the ground, whereby a signal on the signal path drives the third FET and the fourth FET.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• and
• wherein said logic circuit further captures a second static input signal and the first pulse generator is a dual enable ANDing pulse generator that evaluates the first static input signal, the second static input signal, and the at least one clock waveform input signal to generate the first pulse.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• and
• wherein said logic circuit further captures a second static input signal and the first pulse generator is a dual enable ORing pulse generator that evaluates the first static input signal, the second static input signal, and the at least one clock waveform input signal to generate the first pulse.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• and
• a second pulse generator, wherein:
• said logic circuit further captures a second static input signal, a third static input signal and a fourth static input signal;
• the first pulse generator is a dual enable ORing pulse generator that evaluates the first static input signal, the second static input signal, and the at least one clock waveform input signal to generate the first pulse;
• and
• the second pulse generator is a dual enable ORing pulse generator that evaluates the third static input signal, the fourth static input signal, and the at least one clock waveform input signal to generate a second pulse.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• a second pulse generator;
• and
• a third pulse generator, wherein:
• said logic circuit further captures a second static input signal, a third static input signal, a fourth static input signal, a fifth static input signal and a sixth static input signal;
• the first pulse generator is a dual enable ANDing pulse generator that evaluates the first static input signal, the second static input signal, and the at least one clock waveform input signal to generate the first pulse;
• the second pulse generator is a dual enable ANDing pulse generator that evaluates the third static input signal, the fourth static input signal, and the at least one clock waveform input signal to generate a second pulse;
• and
• the third pulse generator is a dual enable ANDing pulse generator that evaluates the fifth static input signal, the sixth static input signal, and the at least one clock waveform input signal to generate a third pulse.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• and
• mousetrap circuitry that produces a second dynamic signal output that is a logic inverse of the first dynamic signal output, wherein:
• said logic circuit further captures a second static input signal;
• and
• the mousetrap circuitry comprises a second pulse generator,
• wherein the second pulse generator evaluates an inverse of the first static input signal, an inverse of the second static input signal and the at least one clock waveform input signal to generate a second pulse, wherein the second pulse is used to determine when to produce the second dynamic signal output.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first pulse, wherein the first pulse is used to determine when to produce a first dynamic signal output;
• and
• replaying circuitry that latches the value of the first dynamic signal output when a stall is detected, wherein the replaying circuitry replays the first dynamic signal output from the latched value.

A method for capturing a static input and converting the static input to a dynamic signal comprising the steps of:

• receiving a first static input signal;
• receiving a clock waveform input signal, wherein the first static input signal and the clock waveform input signal are received in a logic circuit;
• pulse evaluating the first static input signal and the clock waveform input signal, wherein the pulse evaluating step produces a self-timed pulse;
• and
• generating a dynamic signal output based on the pulse evaluation of the first static input signal and the clock waveform input signal.

An apparatus for capturing a static input and converting the static input to a dynamic signal comprising:

• a logic circuit that captures a first static input signal and at least one clock waveform input signal, the logic circuit comprising:
• a first pulse generator, wherein the first pulse generator evaluates the first static input signal and the at least one clock waveform input signal to generate a first self-timed pulse, wherein the first pulse generator includes one or more field-effect transistors;
• and
• additional circuitry for receiving the first self-timed pulse and generating a first dynamic signal output.