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US 6,388,487 B1Granted
Schmitt circuit
AssigneesMitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
InventorShinichi Hirose
Life of this patent
Estimating the term…
Abstract
By turning OFF a PMOS transistor 15a of a feedback inverter 15 as the signal level at an input node 6 gradually changes from the “L” to “H” level, a high-level output from the feedback inverter 15 to an intermediate node 7 is limited, or by tuning OFF an NMOS transistor 15b of the feedback inverter 15 as the signal level at the input node gradually changes from the “H” to “L” level, a low-level output from the feedback inverter 15 to the intermediate node 7 is limited. Hence, the hysteresis width can be narrowed by limiting the output to the intermediate node 7 from the feedback inverter 15 which functions to expand the hysteresis width.
Claims12
A Schmitt circuit comprising:
- an input side inverter which inverts a signal from an input node and outputs it to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node, and
- a hysteresis width control circuit which is actuated in response to a hysteresis width control signal and inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node.
1 more element
A Schmitt circuit comprising:
- an input side inverter which inverts a signal from an input node and outputs it to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- and
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node,
- wherein said feedback inverter comprises:
- an inverter in which a power supply, a first PMOS transistor, a first NMOS transistor and a low power supply are connected in this order, said first PMOS and NMOS transistors having their gates connected to said output node;
- and a switching circuit in which second PMOS and NMOS transistors are connected in opposing relation to each other, said second PMOS and NMOS transistors having their gates connected to said input node, and which limits the intensity of the output signal to said intermediate node via the connection point of said first PMOS and NMOS transistors of said inverter.
4 more elements
A Schmitt circuit comprising:
- a NOR circuit which outputs the NOR of a control signal and a signal from an input node to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node;
- and
- a hysteresis width control circuit which is actuated in response to a hysteresis width control signal and inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node.
2 more elements
A Schmitt circuit comprising:
- a NOR circuit which outputs the NOR of a control signal and a signal from an input node to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- and
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node, wherein said feedback inverter comprises:
- an inverter in which a power supply, a first PMOS transistor, a first NMOS transistor and a low power supply are connected in this order, said first PMOS and NMOS transistors having their gates connected to said output node;
- and a switching circuit in which second PMOS and NMOS transistors are connected in opposing relation to each other, said second PMOS and NMOS transistors having their gates connected to said input node, and which limits the intensity of the output signal to said intermediate node via the connection point of said first PMOS and NMOS transistors of said inverter.
3 more elements
A Schmitt circuit comprising:
- a NAND circuit which outputs the NAND of a control signal and a signal from an input node to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node;
- and
- a hysteresis width control circuit which is actuated in response to a hysteresis width control signal and inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node.
2 more elements
A Schmitt circuit comprising:
- a NAND circuit which outputs the NAND of a control signal and a signal from an input node to an intermediate node;
- an output side inverter which inverts a signal from said intermediate node and outputs it to an output node;
- and
- a feedback inverter which inverts a signal from said output node and outputs it to said intermediate node while at the same time limiting the output intensity of said signal to said intermediate node in accordance with said signal from said input node, wherein said feedback inverter comprises:
- an inverter in which a power supply, a first PMOS transistor, a first NMOS transistor and a low power supply are connected in this order, said first PMOS and NMOS transistors having their gates connected to said output node;
- and a switching circuit in which second PMOS and NMOS transistors are connected in opposing relation to each other, said second PMOS and NMOS transistors having their gates connected to said input node, and which limits the intensity of the output signal to said intermediate node via the connection point of said first PMOS and NMOS transistors of said inverter.
3 more elements
Dependencies are inferred from the claim text.