Load sensing, slew rate shaping, output signal pad cell driver circuit and method
AssigneeLSI Logic Corporation
InventorRichard T. Schultz
Life of this patent
Estimating the term…
Abstract
The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.
Claims22
An output signal pad cell driver circuit of an integrated circuit for controlling the slew rate of a digital logic output signal delivered from an output pad of the integrated circuit in relation to a load connected to the output pad, the output signal occurring in response to an input digital logic signal to said driver circuit, said driver circuit comprises:
- a first timing circuit for generating a first predetermined plurality of first trigger signals which occur in a first sequence at sequentially spaced time intervals with respect to one another;
- a second timing circuit for generating a second predetermined plurality of second trigger signals which occur in a second sequence at sequentially spaced time intervals with respect to one another in the first and second sequences, respectively;
- the first and second predetermined pluralities of trigger signals being equal in number;
- the first trigger signals of the first sequence and the second trigger signals of the second sequence correlating to one another;
- the time intervals between the first trigger signals in the first sequence being different from the time intervals between the second trigger signals in the second sequence;
- the first timing circuit responds to the input signal to initiate the generation of the first plurality of first trigger signals;
- the second timing circuit responds to the output signal under influence of the load connected to the output pad to initiate the generation of the second plurality of second trigger signals;
- a plurality of logic gates, the plurality of logic gates equal in number to the number of first and second trigger signals in the first and second sequences, respectively;
- each logic gate receiving the correlated first and second trigger signals and supplying a selected one of the correlated first and second trigger signals which occupies a predetermined temporal relationship to the other trigger signal received at each logic gate;
- and
- a switching circuit comprising a plurality of drive switches connected to the output pad, each drive switch connected to a different logic gate to receive the selected one of the first and second trigger signals, the selected one of the trigger signals applied from each logic gate controlling the conductivity of each drive switch to establish the slew rate of the output signal.
An output signal pad cell driver circuit of an integrated circuit for controlling the slew rate of a digital logic output signal delivered from an output pad of the integrated circuit in relation to a load connected to the output pad, the output signal occurring in response to an input digital logic signal to said driver circuit, said driver circuit comprises:
- a first timing circuit responsive to a change in the input signal from one logic level to another logic level to initiate generating a plurality of first trigger signals which occur at sequentially spaced time intervals with respect to one another;
- a second timing circuit responsive to a change in the output signal relative to time under influence by the load connected to the output pad to initiate generating a plurality of second trigger signals which occur at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals;
- and
- a switching circuit comprising a plurality of drive switches connected to the output pad and responsive to the first and second trigger signals, the trigger signals controlling the conductivity of the drive switches in relation to the occurrence of those trigger signals to establish the slew rate of the output signal;
- and wherein
- the second timing circuit includes a plurality of timing elements connected in series which each generate a second trigger signal, each series-connected timing element generating its second trigger signal at a time interval after the preceding series-connected timing element generates its second trigger signal;
- and
- the second timing circuit further includes a comparator connected to the output pad and receptive of the output signal, the comparator having a trip point level at which a trip point signal is delivered, and the comparator delivering the trip point signal to the plurality of series-connected timing elements of the second timing circuit.
An output signal pad cell driver circuit of an integrated circuit for controlling the slew rate of a digital logic output signal delivered from an output pad of the integrated circuit in relation to a load connected to the output pad, the output signal occurring in response to an input digital logic signal to said driver circuit, said driver circuit comprises:
- a first timing circuit responsive to a change in the input signal from one logic level to another logic level to initiate generating a plurality of first trigger signals which occur at sequentially spaced time intervals with respect to one another;
- a second timing circuit responsive to a change in the output signal relative to time under influence by the load connected to the output pad to initiate generating a plurality of second trigger signals which occur at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals, the second timing circuit including a plurality of timing elements which each generate a second trigger signal;
- and
- a switching circuit comprising a plurality of drive switches connected to the output pad and responsive to the first and second trigger signals, the trigger signals controlling the conductivity of the drive switches in relation to the occurrence of those trigger signals to establish the slew rate of the output signal;
- and wherein
- the second timing circuit further includes a plurality of comparators connected to receive a signal from the output pad, one comparator connected to each timing element, each comparator having a trip point level at which a trip point signal is delivered, each comparator having a different trip point level from the other trip point levels of the other comparators, and each comparator delivering its trip point signal to its connected timing element at a different time established by its trip point level and the rate of change of the output signal.
A method of controlling the slew rate of a digital logic output signal delivered from an output pad of an integrated circuit relative to a load connected to the output pad, in response to the occurrence of an input digital logic signal, said method comprising:
- generating a first predetermined plurality of first trigger signals in a first sequence at sequentially spaced time intervals with respect to one another, in response to the occurrence of the input signal;
- generating a second predetermined plurality of second trigger signals in a second sequence at sequentially spaced time intervals with respect to one another, in response to the influence of the load connected to the output pad on the output signal;
- generating a number of first trigger signals in the first sequence which is equal to the number of second trigger signals in the second sequence;
- correlating first and second triggers signals at corresponding locations in the first and second sequences;
- establishing the time intervals between the first trigger signals in the first sequence as different from the time intervals between the second trigger signals in the second sequence;
- selecting one of the first and second correlated trigger signals at corresponding locations in the first and second sequences;
- connecting a plurality of conductivity elements to the output pad;
- applying the selected one of the correlated first and second trigger signals to a different conductivity element;
- and
- changing the level of the output signal at the output pad by changing the conductivity of a conductivity element connected to the output pad in relation to the selected one trigger signal applied to the conductivity element.
A method of controlling the slew rate of a digital logic output signal delivered from an output pad of an integrated circuit relative to a load connected to the output pad, in response to the occurrence of an input digital logic signal, said method comprising the steps of:
- generating a plurality of first trigger signals at sequentially spaced time intervals with respect to one another, in response to the occurrence of the input signal;
- generating a plurality of second trigger signals at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals;
- adjusting at least one of the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad;
- selecting one of the pluralities of the first and second signals;
- changing the level of the output signal at the output pad in relation to the occurrence of the selected one plurality of second signals by changing the conductivity of a conductivity element connected to the output pad in relation to each trigger signal;
- and
- counting a predetermined time after the occurrence of the input signal at which to select the one of the pluralities of trigger signals.
An output signal pad cell driver circuit of an integrated circuit for controlling the slew rate of a digital logic output signal delivered from an output pad of the integrated circuit in relation to a load connected to the output pad, the output signal occurring in response to an input digital logic signal to said driver circuit, said driver circuit comprises:
- a first timing circuit responsive to a change in the input signal from one logic level to another logic level to initiate generating a plurality of first trigger signals which occur at sequentially spaced time intervals with respect to one another;
- a second timing circuit responsive to a change in the output signal relative to time under influence by the load connected to the output pad to initiate generating a plurality of second trigger signals which occur at sequentially spaced time intervals with respect to one another and at time intervals different from the time intervals of the first trigger signals;
- and
- a switching circuit comprising a plurality of drive switches connected to the output pad and responsive to the first and second trigger signals, the trigger signals controlling the conductivity of the drive switches in relation to the occurrence of those trigger signals to establish the slew rate of the output signal;
- and wherein the second timing circuit further includes:
- a first plurality of fast delay elements connected in series and a second plurality of slow delay elements connected in series;
- a multiplexer receptive of the trigger signals generated by the first and second pluralities of series-connected fast and slow delay elements, the multiplexer operatively selecting one of the trigger signals from the fast delay elements or the trigger signals from the slow delay elements for application to the switching circuit.
Dependencies are inferred from the claim text.