Delay-locked loop circuit having master-slave structure

A delay-locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal, comprising:

• a phase comparator for comparing the phase of the external clock signal and the phase of a feedback signal and generating a detection signal corresponding to a phase difference between the external clock signal and the feedback signal, wherein the external clock is applied directly to the phase comparator;
• a delay controller for receiving the detection signal and generating a first delay control signal;
• a first voltage controlled delay part for delaying the external clock signal by a predetermined delay time based on the voltage of the first delay control signal and then generating the feedback signal, wherein the external clock is applied directly to the phase comparator;
• an analog filter for removing a high frequency component from the first delay control signal and generating a second delay control signal;
• and
• a second voltage controlled delay part for delaying the external clock signal by the predetermined delay time based on the voltage of the second delay control signal and generating the internal clock signal.

A delay-locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal, comprising:

• a phase comparator for comparing the phase of the external clock signal and the phase of a feedback signal and generating a detection signal corresponding to a phase difference between the external clock signal and the feedback signal;
• a delay controller for receiving the detection signal and generating first and second delay control signals;
• a coarse delay part for delaying the external clock signal by a predetermined first delay time in response to the first delay control signal and generating a delay signal;
• a fine delay part for delaying the delay signal by a predetermined second delay time in response to the second delay control signal and then generating the feedback signal;
• a low-pass filter for removing a high frequency component from the second delay control signal and generating a third delay control signal;
• and
• a slave delay part for delaying the delay signal by the second delay time in response to the third delay control signal and generating the internal clock signal.