US 6,388,484 B1Granted

Clock control circuit

AssigneeKabushiki Kaisha Toshiba

InventorsMasahiro Kamoshida, Haruki Toda, Tsuneaki Fuse, Yukihito Oowaki

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Abstract

In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes “H” while pulse s is “L” without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer. As each delay element of forward-pulse delay line and rearward-pulse delay line is configured with one-gate circuits, propagation time of forward pulse and rearward pulse can be adjusted to the time (τ−A) with high accuracy to improve synchronization accuracy.

Claims14

Dependent claims

A clock control circuit, comprising:

a forward-pulse delay line which is configured by cascading delay elements in a first number of stages;
a rearward-pulse delay line which is configured by cascading delay elements in a second number of stages;
an input device for taking in a first clock signal and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal;
a pulse generating device including a forward-pulse generating device for generating a forward pulse by delaying said second clock signal as much as second delay time;
a control circuit, connected to said delay elements of said forward-pulse delay line and said rearward-pulse delay line, which controls a period of time for said forward pulse to propagate in said forward-pulse delay line, controls said forward-pulse delay line to be initialized, controls a rearward pulse to be produced in said rearward-pulse delay line and controls a period of time for said rearward-pulse to propagate in said rearward-pulse delay line;
said pulse generating device generating a control pulse, which is synchronized with said second clock signal, using said second clock signal and forward pulse from said forward-pulse generating device, inputting said control pulse to said control circuit and controlling the operation of said control circuit;
and
an output device for outputting a third clock signal, which is synchronized with said first clock signal by delaying said rearward pulse outputted from said rearward-pulse delay line as much as third delay time.

5 more elements

A clock control circuit, comprising:

a receiver for taking in a first clock signal, and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal;
a pulse generating device including a forward-pulse generating device for generating a forward pulse by delaying said second clock signal as much as a second delay time;
a forward-pulse delay line which is configured by cascading delay elements in a first number of stages;
a rearward-pulse delay line which is configured by cascading delay elements in a second number of stages;
a control circuit, connected to said delay elements of said forward-pulse delay line and said rearward-pulse delay line;
said pulse generating device generating a control pulse, which is synchronized with said second clock signal, using said second clock signal and forward pulse from said forward-pulse generating device, inputting said control pulse to said control circuit and controlling the operation of said control circuit;
and
an output buffer for delaying said rearward pulse outputted from said rearward-pulse delay line as much as a third delay time, and outputting a third clock signal which is synchronized with said first clock signal,
wherein said control circuit controls said forward pulse to propagate in said forward-pulse delay line until said control pulse is inputted, controls said forward-pulse delay line to be initialized, controls a rearward pulse to be produced in said rearward-pulse delay line and controls a period of time for said rearward-pulse to propagate in said rearward-pulse delay line.

6 more elements

Dependencies are inferred from the claim text.