DLL lock scheme with multiple phase detection

A delay lock loop comprising:

• a delay line including an input and an output, a first clock signal being received at the input and a second clock signal including a delayed first clock signal at the output;
• at least two phase detectors, each receiving the first clock signal and the second clock signal, the phase detectors for determining a phase difference between the first clock signal and the second clock signal in a specified phase difference range and outputting a control signal in accordance with the phase difference;
• and
• an adjustment circuit coupled to outputs of the phase detectors for interpreting the control signals from all of the phase detectors, the adjustment circuit adapted to determine whether to increment, decrement or lock the delay line and to determine a size of the increment or decrement to reduce the phase difference between the first and second clock signals by combining the control signals of the phase detectors to provide a single adjustment magnitude and direction for the delay line.

A method for adjusting delay in a delay lock loop, comprising the steps of:

• providing a delay lock loop including a plurality of phase detectors each receiving a first clock signal and a second clock signal, each phase detector including a specified delay range for detecting phase differences between the first and second clock signals in that range, and a delay line including an input and an output, the first clock signal is received at the input and the second clock signal includes a delayed first clock signal;
• determining phase differences for each phase detector;
• outputting control signals from the phase detectors;
• determining whether to increment, decrement or lock the delay lock loop by combining the control signals of the phase detectors;
• if an increment or decrement is determined, determining an amount of delay to be incremented or decremented by employing the control signals of all the phase detectors;
• and
• adjusting the delay line in accordance with the control signals.

A delay lock loop comprising:

• a plurality of phase detectors each receiving a first clock signal and a second clock signal, the second clock signal including a delayed first clock signal;
• each phase detector including a specified delay range for detecting phase differences between the first and second clock signals in that range;
• and
• a delay line including an input and an output, the first clock signal being received at the input, wherein an amount of delay applied to the first clock signal is adjusted in the delay line in accordance with control signals of the phase detectors, wherein the plurality of phase detectors includes five phase detectors.

A delay lock loop comprising:

• a plurality of phase detectors each receiving a first clock signal and a second clock signal, the second clock signal including a delayed first clock signal;
• each phase detector including a specified delay range for detecting phase differences between the first and second clock signals in that range;
• and
• a delay line including an input and an output, the first clock signal being received at the input, wherein an amount of delay applied to the first clock signal is adjusted in the delay line in accordance with control signals of the phase detectors, wherein the plurality of phase detectors includes at least three phase detectors.