US 6,388,481 B1Granted

Oscillator control circuitry for phase lock loop providing enhanced phase noise and spurious signal performance

AssigneeNational Semiconductor Corporation

InventorsKim Yeow Wong, David Lindsay Broughton, Jeffrey Mark Huard

Life of this patent

Estimating the term…

Loading patent…

Abstract

Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (“pump up”) or sink (“pump down”) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

Claims16

Dependent claims

An apparatus including oscillator control circuitry for a phase lock loop, comprising:

phase detection circuitry, responsive to a reference signal, an oscillator feedback signal and a charge pump feedback signal, that provides first and second phase signals indicative of a phase difference between said reference and oscillator feedback signals with respective assertion states responsive to said phase difference and respective deassertion states responsive to said charge pump feedback signal;
control signal generator circuitry, coupled to said phase detection circuitry and responsive to said first and second phase signals, that provides
a first pump control signal with assertion and deassertion states corresponding to and time-delayed from said first phase signal assertion and deassertion states,
a first bias control signal with assertion and deassertion states responsive to said first phase signal and said first pump control signal,
a second pump control signal with assertion and deassertion states corresponding to and time-delayed from said second phase signal assertion and deassertion states, and
a second bias control signal with assertion and deassertion states responsive to said second phase signal and said second pump control signal;
bias control circuitry, coupled to said control signal generator circuitry and responsive to said first and second bias control signals, that provides first and second bias enablement signals with assertion and deassertion states;
and
charge pump circuitry, coupled to said bias control circuitry and said control signal generator circuitry and responsive to said first and second bias enablement signals and said first and second pump control signals, that provides a composite output current signal and said charge pump feedback signal, wherein
said composite output current signal includes an output source current component substantially coincident with said first bias enablement and pump control signal assertion states and includes an output sink current component substantially coincident with said second bias enablement and pump control signal assertion states, and
said charge pump feedback signal includes an assertion state responsive to a coincidence of said output source and sink current components.

8 more elements

An apparatus including oscillator control circuitry for a phase lock loop, comprising:

phase detector means for receiving a reference signal, an oscillator feedback signal and a charge pump feedback signal and in response thereto generating first and second phase signals indicative of a phase difference between said reference and oscillator feedback signals with respective assertion states responsive to said phase difference and respective deassertion states responsive to said charge pump feedback signal;
control signal generator means for receiving said first and second phase signals and in response thereto generating
a first pump control signal with assertion and deassertion states corresponding to and time-delayed from said first phase signal assertion and deassertion states,
a first bias control signal with assertion and deassertion states responsive to said first phase signal and said first pump control signal,
a second pump control signal with assertion and deassertion states corresponding to and time-delayed from said second phase signal assertion and deassertion states, and
a second bias control signal with assertion and deassertion states responsive to said second phase signal and said second pump control signal;
bias controller means for receiving said first and second bias control signals and in response thereto generating first and second bias enablement signals with assertion and deassertion states;
and
charge pump means for receiving said first and second bias enablement signals and said first and second pump control signals and in response thereto generating a composite output current signal and said charge pump feedback signal, wherein
said composite output current signal includes an output source current component substantially coincident with said first bias enablement and pump control signal assertion states and includes an output sink current component substantially coincident with said second bias enablement and pump control signal assertion states, and
said charge pump feedback signal includes an assertion state responsive to a coincidence of said output source and sink current components.

8 more elements

Dependencies are inferred from the claim text.