Method and apparatus for reducing the lock time of DLL

A method of synchronizing a delay locked loop (DLL), comprising:

• initializing a plurality of delay line shift bits to an initial value;
• propagating a rising edge of a first input clock pulse through a delay line;
• toggling the shift bits to a different toggled value as the rising edge of the first clock pulse reaches each respective shift bit;
• propagating a rising edge of a second consecutive input clock pulse through the delay line;
• re-toggling the shift bits to their initial value as the rising edge of the second clock pulse reaches each respective shift bit;
• detecting when the rising edge of the first clock pulse reaches an end of the delay line;
• halting the re-toggling of the shift bits when the rising edge of the first clock pulse reaches the end of the delay line;
• and
• starting a lock sequence for the DLL at a transition between toggled and re-toggled shift bits.

A method of synchronizing a delay locked loop (DLL), comprising:

• initializing a plurality of delay line shift bits to an initial value;
• propagating an edge of a first input clock pulse through a delay line;
• toggling the shift bits to a different toggled value as the first rising edge reaches each respective shift bit;
• propagating an edge of a second consecutive input clock pulse through the delay line;
• re-toggling the shift bits to their initial value as the second rising edge reaches each respective shift bit;
• preventing further re-toggling of the shift bits when the first rising edge reaches an end of the delay line;
• and
• starting a lock sequence for the DLL at a transition between toggled and re-toggled shift bits.

A method of improving synchronization time in a delay locked loop (DLL), comprising:

• initializing a plurality of shift bits in a delay line to a binary one;
• toggling each respective shift bit to a binary zero as a first clock signal is passed through the delay line;
• re-toggling each respective shift bit back to a binary one as a second clock signal is passed through the delay line;
• detecting an edge of the first clock signal at an end of the delay line;
• preventing further toggling of the shift bits at the detection of the edge of the first clock signal;
• and
• beginning clock synchronization at a transition between the toggled and re-toggled shift bits.

A method of reducing lock time of a delay locked loop (DLL), comprising:

• initializing a circuit to measure a length of an input clock period relative to a path length through the DLL;
• propagating a first clock edge through a delay line having a plurality of delay elements, a plurality of shift bits, and an input end and an output end, each shift bit corresponding to one of the plurality of delay elements;
• toggling the respective shift bit of each delay element as the first clock edge passes each delay element;
• propagating a second clock edge through the delay line;
• re-toggling the respective shift bit of each delay element as the second clock edge passes each delay element;
• preventing further re-toggling of the shift bits upon detection of the first clock edge at a phase detection circuit at the output end of the delay line;
• and
• initiating a lock sequence for the DLL at the transition point between toggled and re-toggled shift bits.

A method for estimating lock sequence startup position in a delay locked loop (DLL), comprising:

• disabling a plurality of enabled shift bits upon triggering by a first rising clock edge of a clock signal;
• enabling a portion of the disabled shift bits upon triggering by a second rising clock edge of a the clock signal;
• and
• starting a lock sequence for the DLL at a transition between enabled and disabled shift bits.

A method for reducing lock time in a delay locked loop (DLL), comprising:

• initializing each of a plurality of delay elements in a delay line to an enabled state;
• propagating a first pulse of a clock signal through the delay line;
• disabling each of the plurality of delay elements when the first clock pulse passes through each delay element;
• propagating a second pulse of the clock signal through the delay line;
• re-enabling each of the plurality of the delay elements when the second clock pulse passes through each delay element;
• locking the state of each delay element when the first clock pulse reaches an end of the delay line;
• and
• starting a synchronization sequence at a transition point between disabled and re-enabled delay elements in the delay line.

A delay locked loop (DLL), comprising:

• a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on a rising edge of a clock signal;
• delay line circuitry to pass two consecutive rising clock signal edges to the delay line;
• and
• edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.

A delay locked loop, comprising:

• a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on a rising edge of a clock signal;
• an input clock buffer to receive an input clock signal;
• a normally open signal gate connected to an output of the input clock buffer to detect a first edge of a first clock signals and a second edge of the clock signal and to pass the first and the second clock signals to the delay line;
• a phase detector connected to an output end of the delay line to detect the edge of the first edge;
• and
• shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the first edge at the output end of the delay line.

A delay locked loop, comprising:

• an adjustable delay chain having a plurality of delays and a plurality of shift bits, each shift bit corresponding to one of the plurality of delays, each shift bit operable in a first state and a second state, wherein the states are toggled by a clock signal edge passing through its respective delay;
• an edge detection circuit connected to an input of the delay line to pass two clock edges to the delay line;
• a phase detector connected to an output of the delay line to detect when the first edges reaches the output of the delay line;
• and
• shift bit logic connected between the phase detector and the shift bits to halt the toggling of shift bits when the first edge reaches the output of the delay line.

An integrated circuit, comprising:

• first and second sub-circuits operatively connected to communicate with one another on a synchronized schedule;
• and
• a delay locked loop (DLL) connected to synchronize the first and the second sub-circuits, the DLL comprising:
• a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on detection of a rising edge of a clock signal;
• delay line circuitry to pass two consecutive rising clock signal edges to the delay line;
• and
• edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.

An integrated circuit, comprising:

• first and second sub-circuits operatively connected to synchronize to an external clock;
• and
• a delay locked loop (DLL) connected to synchronize the first and the second sub-circuits, the DLL comprising:
• a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit in response to a rising edge of a clock signal;
• delay line circuitry to pass two consecutive rising clock signal edges to the delay line;
• and
• edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.