Single phase edge trigger register

A method for maintaining logic state stored in a storage device comprising:

• precharging at least two complimentary nodes in said storage device during a precharge stage;
• receiving an input data during an evaluation stage;
• ignoring said input data when output data is stabilized during said evaluation stage;
• storing a logic state in said storage device in response to said input data;
• and
• providing at least one conductive path to limit one store per each said evaluation stage.

A device for performing edge trigger register comprising:

• a storage cell containing a plurality of complimentary nodes;
• a precharge circuit coupled to said storage cell for precharging at least one pair of said complimentary nodes;
• an output holder coupled to said storage cell for storing an output value;
• an input circuit coupled to said storage cell for setting up logic states at said complimentary nodes in response to said input data;
• and
• circuit coupled to said storage cell providing additional discharge channels to limit one latch at said complimentary nodes per each evaluation stage, wherein said storage includes a logic function.

A device for performing edge trigger register comprising:

• a storage cell containing a plurality of complimentary nodes;
• a precharge circuit coupled to said storage cell for precharging at least one pair of said complimentary nodes;
• an input circuit coupled to said storage cell for setting up logic states at said complimentary nodes in response to said input data;
• circuit coupled to said storage cell providing additional discharge channels to limit one latch at said complimentary nodes per each evaluation stage, wherein said storage includes a logic function;
• and
• wherein said discharge circuit causes said input data to be ignored when logic states are latched in said complimentary nodes during said evaluation stage.

An apparatus for maintaining logic state stored in a storage device comprising:

• means for precharging at least two complimentary nodes during a precharge stage;
• means for holding an output value in a storage device during said precharge stage;
• means for receiving input data during an evaluation stage;
• means for storing a logic state at said complimentary nodes in response to said input data;
• and
• means for providing at least one conductive path to one store per each said evaluation stage.

An apparatus for maintaining logic state stored in a storage device comprising:

• means for precharging at least two complimentary nodes during a precharge stage;
• means for receiving input data during an evaluation stage;
• means for storing a logic state at said complimentary nodes in response to said input data;
• means for providing at least one conductive path to one store per each said evaluation stage;
• and
• means for causing said input data to be ignored when logic states are latched at said complimentary nodes during said evaluation stage.