US 6,388,470 B1 · High voltage CMOS signal driver with minimum power dissipation

Abstract

The system and method facilitates the transmission of relatively high voltage signals via a thin oxide gate CMOS device without an excessively detrimental electric field build up across the thin oxide layers forming a gate in a CMOS device. The high voltage CMOS thin oxide gate system and method provides a degradation repression bias voltage signal to the thin oxide gate of the CMOS device. The degradation repression bias voltage signal establishes a differential voltage potential between the source and drain components of the thin oxide gate output CMOS device and the gate component of the thin oxide gate output CMOS device. The degradation repression bias voltage signal is maintained at a level that prevents that excessively detrimental electric field stresses are not induced in oxide layers that form the thin oxide gate in the output CMOS device. The System and method does not require additional power supplies or reference voltages and does not cause the thin gate oxide device to dissipate additional power in a static (non-switching) state.

Claims13

Dependent claims

A high voltage output CMOS thin oxide gate signal driver system comprising:

an output CMOS device adapted to transmit a high voltage signal;
a bias voltage range limiter coupled to said output CMOS device, said bias voltage range limiter adapted to confine a gate degradation repression bias voltage signal within a range that results in an acceptable voltage differential from a gate of said output CMOS device to a source and drain of said output CMOS device that is within electric field stress tolerance limitations of said output CMOS device;
a pull down component coupled to said output CMOS device, said pulldown component adapted to pull a signal down;
a bias voltage level driver coupled to said output CMOS device;
said bias voltage level driver adapted to actively drive said gate degradation repression bias voltage signal to an acceptable level that results in a voltage differential from the gate of said output CMOS device to the source and drain of said output CMOS device that is within electric field stress tolerance limitations of said output CMOS device;
and
a high voltage input component coupled to said bias voltage level driver, said high voltage input component configured as an input receiver adapted to provide a feedback signal to said bias voltage level driver.

4 more elements

A high voltage CMOS thin oxide gate signal driver method comprising the steps of:

applying a relatively high voltage output signal to a source component of a thin oxide gate CMOS device;
supplying a degradation repression bias voltage signal to a gate of said thin oxide gate CMOS device;
maintaining said degradation repression bias voltage signal so that a differential voltage potential between said source component of said thin oxide gate CMOS device and said gate component of said thin oxide gate CMOS device does not result in excessively detrimental electric field stresses in oxide layers that form said thin oxide gate;
controlling said degradation repression bias voltage signal so that said degradation repression bias voltage signal does not reach a voltage level that results in said thin oxide gate CMOS device incidentally turning off;
and
driving said degradation repression bias voltage signal actively and tightly holding said degradation repression bias voltage signal.

3 more elements

Dependencies are inferred from the claim text.

High voltage CMOS signal driver with minimum power dissipation

Life of this patent

High voltage CMOS signal driver with minimum power dissipation

Life of this patent

Abstract

Claims13