Reconfigurable integrated circuit with integrated debussing facilities and scalable programmable interconnect

A single integrated circuit comprising a plurality of logic elements (LEs) for generating a plurality of output signals in response to a plurality of input signals correspondingly applied to the LEs, and a scan register coupled to the LEs for serially capturing and outputting a trace record of all signal state values of the LEs in a particular clock cycle of an operating clock outside the integrated circuit, the scan register being provided with a scan clock appropriately scaled to the operating clock, wherein

• each LE further includes a multiple input-single output truth table for generating a first intermediate output signal in response to a first set of input signals;
• a first selector coupled to the truth table and the context bus for selecting either the first intermediate output signal, or the output of the LE fedback to the first selector, and outputting the selected signal;
• and
• a first control circuit coupled to the first selector for controlling the first selector.

A single integrated circuit comprising a plurality of logic elements (LEs) for generating a plurality of output signals in response to a plurality of input signals correspondingly applied to the LEs, and trigger circuitry coupled to the LEs for conditionally generating at least one trigger value depending on the signal state values of the LEs, wherein

• each LE further includes a multiple input-single output truth table for generating a first intermediate output signal in response to a first set of input signals;
• a first selector coupled to the truth table and the context bus for selecting either the first intermediate output signal, or the output of the LE fedback to the first selector, and outputting the selected signal;
• and
• a first control circuit coupled to the first selector for controlling the first selector.

An integrated circuit comprising:

• a plurality of reconfigurable logic elements (LE);
• a plurality of input/output (I/O) pin;
• a first network of programmable interconnects having a first plurality of subsets of programmable interconnects correspondingly coupled to subsets of the reconfigurable LEs;
• and
• a second network of programmable interconnects coupled to the first network of programmable interconnects and the plurality of I/O pins.