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US 6,388,464 B1Granted
Configurable memory for programmable logic circuits
AssigneeCypress Semiconductor Corporation
InventorsTimothy M. Lacey, David L. Johnson
Life of this patent
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Abstract
An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
Claims18
An apparatus comprising:
- a memory device configured to:
- receive one or more inputs from a first bus and a second bus;
- present one or more outputs to said first bus and said second bus;
- and
- operate in one or more modes in response to one or more control signals;
- and
- a programmable logic circuit configured to generate said control signals.
4 more elements
An apparatus comprising:
- means for configuring a memory device to:
- receive one or more inputs from a first bus and a second bus;
- present one or more outputs to said first bus and said second bus;
- and
- operate in one or more modes in response to one or more control signals;
- and
- means for programmably generating said control signals.
4 more elements
A method of laying out a programmable logic device comprising the steps of:
- placing a first routing channel parallel to a first axis;
- placing a second routing channel parallel to a second axis;
- and
- connecting one or more inputs and one or more outputs of a memory device, configured to operate in one or more modes in response to one or more control signals generated by said programmable logic device, to said first and said second routing channels.
1 more element
Dependencies are inferred from the claim text.