Alternate timing wafer burn-in method
AssigneeUnited Microelectronics Corp.
InventorsWalx Fang, Charlie Han
Life of this patent
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Abstract
An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.
Claims5
An alternate-timing burn-in method for testing a memory unit on a wafer, comprising the steps of:
- generating a first bit line voltage clocking signal and sending the signal to one terminal of the memory unit;
- and
- generating a second bit line voltage clocking signal and sending the signal to the other terminal of the memory unit,
- wherein the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.
An alternate-timing burn-in method for testing a capacitor on a wafer, comprising the steps of:
- generating a first bit line voltage clocking signal and sending the signal to one terminal of the capacitor;
- and
- generating a second bit line voltage clocking signal and sending the signal to the other terminal of the capacitor,
- wherein the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.
Dependencies are inferred from the claim text.