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US 6,388,295 B1Granted
Semiconductor device and method of manufacturing the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTomohiro Yamashita, Yoshinori Okumura, Atsushi Hachisuka, Shinya Soeda
Life of this patent
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Abstract
The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.
Claims20
A semiconductor device comprising:
- a semiconductor layer of a first conductivity type;
- a first impurity region of a second conductivity type formed at a main surface of said semiconductor layer and having a first impurity concentration peak;
- a second impurity region of the first conductivity type formed at the main surface of said semiconductor layer, located within a planar region provided with said first impurity region, and having a second impurity concentration peak at a smaller depth than said first impurity concentration peak;
- a third impurity region of the second conductivity type formed at the main surface of said semiconductor layer, located within the planar region provided with said first impurity region, surrounding said second impurity region, and having a third impurity concentration peak at a smaller depth than the first impurity concentration peak;
- a fourth impurity region of the second conductivity type formed at the main surface of said semiconductor layer, located in a region spaced from said first impurity region, and having a fourth impurity concentration peak;
- a fifth impurity region of the first conductivity type formed at the main surface of said semiconductor layer, located within a planar region provided with said fourth impurity region, and having a fifth impurity concentration peak at a smaller depth than said second and fourth impurity concentration peaks;
- a sixth impurity region of the second conductivity type formed at the main surface of said semiconductor layer, located within a planar region provided with said fourth impurity region, surrounding said fifth impurity region and having a sixth impurity concentration peak at a smaller depth than the fourth impurity concentration peak;
- a first field-effect element of the second conductivity type formed at the main surface of said second impurity region;
- and
- a second field-effect element of the second conductivity type formed at the main surface of said fifth impurity region.
7 more elements
A semiconductor device comprising:
- a semiconductor layer of a first conductivity type;
- a first impurity region of a second conductivity type formed at a main surface of said semiconductor layer and having a first impurity concentration peak;
- a second impurity region of the first conductivity type formed at the main surface of said semiconductor layer provided with said first impurity region, surrounded entirely by said first impurity region and having a second impurity concentration peak at a smaller depth than said first impurity concentration peak;
- a third impurity region of the first conductivity type formed at the main surface of said semiconductor layer, located in a region between said first and second impurity regions, surrounding said second impurity region, and having a third impurity concentration peak at a smaller depth than said second impurity concentration peak;
- and
- a first field-effect element of the second conductivity type formed at the main surface of said second impurity region.
3 more elements
A method of manufacturing a semiconductor device comprising the steps of:
- forming a first impurity region of a second conductivity type having a first impurity concentration peak at a main surface of a semiconductor layer of a first conductivity type;
- forming a second impurity region of the second conductivity type arranged at the main surface of said semiconductor layer, located in a region different from said first impurity region and having a second impurity concentration peak;
- forming a third impurity region of the first conductivity type arranged at the main surface of said semiconductor layer provided with said first impurity region, and having a third impurity concentration peak at a smaller depth than said first impurity concentration peak;
- forming a fourth impurity region of the first conductivity type formed at the main surface of said semiconductor layer provided with said second impurity region, and having a fourth impurity concentration peak at a smaller depth than said second impurity concentration peak;
- forming a fifth impurity region of the second conductivity type arranged at the main surface of said semiconductor layer provided with the first impurity region, and having a fifth impurity concentration peak at a smaller depth than said first and third impurity concentration peaks, and a sixth impurity region of the second conductivity type arranged at the main surface of said semiconductor layer provided with said second impurity region, surrounding said fourth impurity region and having said fifth impurity concentration peak;
- forming a first element of the second conductivity type at the main surface of said third impurity region;
- and
- forming a second element of the second conductivity type at the main surface of said fourth impurity region.
5 more elements
Dependencies are inferred from the claim text.