US 6,388,286 B1Granted

Power semiconductor devices having trench-based gate electrodes and field plates

AssigneeNorth Carolina State University

InventorBantval Jayant Baliga

Life of this patent

Estimating the term…

Loading patent…

Abstract

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation. Methods according to the present invention also include the steps of forming a trench in a semiconductor substrate and then forming an insulated source electrode in and adjacent a bottom of the trench by forming a first electrically insulating layer on a bottom and sidewall of the trench, then forming a first electrically conductive layer on the first electrically insulating layer and then forming a second electrically insulating layer on the first electrically conductive layer using a thermal oxidation technique, for example. An insulated gate electrode is then formed in and adjacent a top of trench. Steps are also provided to form a source region of first conductivity type in the semiconductor substrate and form a second source electrode electrically connected to the source region and the insulated source electrode.

Claims11

Dependent claims

A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;
a drift region of first conductivity type in said substrate;
first and second trenches that extend in the first face of said substrate and define an inactive transition region mesa therebetween into which said drift region extends;
a vertical MOSFET in an active region within said substrate, said vertical MOSFET comprising an insulated gate electrode in said second trench, and a source region of first conductivity type and a base region of second conductivity type that extend adjacent a sidewall of said second trench, said base region forming a P-N rectifying junction with said drift region at a first depth relative to the first face;
a breakdown shielding region of second conductivity type that extends in the transition region mesa and adjacent the first face and defines a P-N rectifying junction with said drift region;
a field plate insulating region lining a sidewall and bottom of said first trench;
and
a field plate extending in said first trench and on said field plate insulating region;
wherein said breakdown shielding region has a maximum depth relative to the first face that is greater than the first depth and is less than a depth of said first and second trenches;
and
wherein said breakdown shielding region also has a sufficient second conductivity type doping concentration therein that in combination with the maximum depth causes avalanche breakdown to occur in the inactive transition region mesa before it occurs at the P-N junction within the active region, when the device is biased into reverse breakdown.

8 more elements

A semiconductor switching device, comprising:

a semiconductor substrate having first and second opposing faces;
a drain region of first conductivity type in said substrate, adjacent the second face;
a drift region of first conductivity type in said substrate, said drift region forming a nonrectifying junction with said drain region and having a graded first conductivity type doping concentration therein which decreases in a direction from said drain region towards the first face;
a first trench in said substrate at the first face, said first trench having first and second opposing sidewalls which extend from the first face into said drift region;
a second trench in said substrate at the first face, said second trench having first and second opposing sidewalls which extend from the first face into said drift region, said second sidewall of said first trench and said second sidewall of said second trench defining a transition region mesa therebetween into which said drift region extends;
a source region of first conductivity type in said substrate, said source region extending opposite the first sidewall of said first trench and adjacent the first face;
a base region of second conductivity type in said substrate, said base region extending between said source region and said drift region and forming a first P-N junction with said source region and a second P-N junction with said drift region;
a breakdown shielding region of second conductivity type that extends in the transition region mesa and is electrically connected to said source region, said breakdown shielding region having a maximum depth relative to the first face that is greater than a depth of the second P-N junction and is less than a depth of said first and second trenches and also having a sufficient second conductivity type doping concentration therein that in combination with the maximum depth causes avalanche breakdown to occur in the transition region mesa before it occurs at the second P-N junction when the device is sufficiently reverse-biased;
a gate insulating region of nonuniform thickness lining the first and second sidewalls and a bottom of said first trench;
a first field plate insulating region lining the first and second sidewalls and a bottom of said second trench;
a gate electrode in said first trench, on said gate insulating region;
and
a field plate in said second trench, on said first field plate insulating region.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/377,006Filed 18 Aug 1999 · continuation in part
Priority: 26 Oct 1998
Granted: 14 May 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 8/605
Schottky-barrier diodes: of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]
H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 62/157
Drain regions of DMOS transistors: impurity concentrations or distributions