US 6,388,284 B2Granted

Capacitor structures

AssigneeMicron Technology, Inc.

InventorsHoward E. Rhodes, Lyle D. Breiner, Philip J. Ireland, Trung Tri Doan, Gurtej S. Sandhu, Sujit Sharan

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Abstract

Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.

Claims29

Dependent claims

A capacitor comprising:

a substrate having a node location;
a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material;
an insulative layer disposed over the substrate and on the insulative material, the insulative layer having an opening over the node location and the insulative material;
a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening in contacting relationship with both the insulative layer and the insulative material covering the gate sidewall, and operably connected with the node location;
a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area;
a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity;
a capacitor dielectric layer over the conductive material layer;
and
a capacitor plate over the capacitor dielectric layer.

6 more elements

A capacitor comprising:

a substrate having a node location;
a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material;
an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location;
a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location, the first polysilicon material layer having a planar uppermost surface;
a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area, the second polysilicon material layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the first polysilicon material layer;
a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the second polysilicon material layer and the planar uppermost surface of the first polysilicon material layer;
a capacitor dielectric layer over the conductive material layer;
and
a capacitor plate over the capacitor dielectric layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/754,924Filed 3 Jan 2001 · division
Priority: 25 Jun 1999
Published: US 2001/0001210 A117 May 2001
Granted: 14 May 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 1/712
Having non-planar surfaces, e.g. formed by texturisation: being rough surfaces, e.g. using hemispherical grains
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 1/714
Having non-planar surfaces, e.g. formed by texturisation: having horizontal extensions

Family

Application09/339,890Parent of this division · filed 25 Jun 1999
US 6,291,289 B1Parent of this division
US 2001/0001210 A1Published application
US 2001/0012656 A1Published application
US 6,388,284 B2This patent

From the US filing history. Foreign family members aren’t listed.