Triple metal line 1T/1C ferroelectric memory device and method for fabrication thereof

A one transistor and one capacitor ferroelectric memory device comprising:

• a transistor that has a gate electrode and source/drain regions formed on a semiconductor substrate;
• a first metal line electrically connected to one of the source/drain regions through a first interlayer insulating layer;
• a second interlayer insulating layer formed on the first interlayer insulating layer and the first metal line;
• a ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the other of the source/drain regions through a contact plug formed in the second and first interlayer insulating layers;
• wherein the ferroelectric capacitor includes:
• an adhesion layer formed on the second interlayer insulating layer;
• an oxidation barrier layer formed on the adhesion layer;
• a lower electrode formed on the oxidation barrier layer;
• a ferroelectric film formed on the lower electrode;
• and
• an upper electrode formed on the ferroelectric film;
• a diffusion barrier layer formed on the ferroelectric capacitor;
• a third interlayer insulating layer formed on the second interlayer insulating layer and the ferroelectric capacitor;
• a second metal line, which is electrically connected to the gate electrode, formed on the third interlayer insulating layer;
• a fourth interlayer insulating layer formed on the third interlayer insulating layer and the second metal line;
• and
• a third metal line, which is electrically connected to the ferroelectric capacitor, formed on the fourth interlayer insulating layer.