Electronic assembly with trench structures and methods of manufacture

A substrate for mounting an integrated circuit comprising:

• a plurality of non-conductive layers, at least some of the layers comprising a plurality of traces, vias, and trenches;
• and
• a plurality of lands on a surface thereof and coupled to a group of the traces, vias, and trenches;
• wherein at least one of the plurality of lands is to couple to a first potential, wherein at least another one of the first plurality of lands is to couple to a second potential, wherein a first group of trenches is to conduct the first potential;
• and wherein a second group of trenches is to conduct the second potential.

An electronic package comprising:

• a substrate comprising:
• a plurality of non-conductive layers, at least some of the layers comprising a plurality of traces, vias, and trenches;
• p2 a first plurality of lands on a first surface thereof and coupled to a first group of traces, vias, and trenches;
• and
• a second plurality of lands on a second surface thereof and coupled to a second group of traces, vias, and trenches;
• wherein at least one of the first plurality of lands and one of the second plurality of lands are to couple to a first potential, wherein at least another one of the first plurality of lands and another one of the second plurality of lands are to couple to a second potential, wherein a first group of trenches is to conduct the first potential;
• and wherein a second group of trenches is to conduct the second potential;
• and
• an integrated circuit coupled to the first plurality of lands.

An electronic system comprising:

• a bus coupling components in the electronic system;
• a display coupled to the bus;
• external memory coupled to the bus;
• and
• a processor coupled to the bus and comprising an electronic assembly including:
• a substrate comprising:
• a plurality of non-conductive layers, at least some of the layers comprising a plurality of traces, vias, and trenches;
• a first plurality of lands on a first surface thereof and coupled to a first group of traces, vias, and trenches;
• and
• a second plurality of lands on a second surface thereof and coupled to a second group of traces, vias, and trenches;
• wherein at least one of the first plurality of lands and one of the second plurality of lands are to couple to a first potential, wherein at least another one of the first plurality of lands and another one of the second plurality of lands are to couple to a second potential, wherein a first group of trenches is to conduct the first potential;
• and wherein a second group of trenches is to conduct the second potential;
• and
• an integrated circuit coupled to the first plurality of lands.

A method for fabricating a substrate, the method comprising:

• forming a core region of the substrate;
• forming a plurality of vias in the core region;
• forming a plurality of trenches in the core region;
• applying a conductive material to the vias and trenches;
• and
• forming a first buildup region above the core region.