Method of forming barrier and seed layers for electrochemical deposition of copper
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Shau-Lin Shue
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Abstract
A process in the fabrication of integrated circuits has been developed for copper diffusion barrier layer and copper seed layer. The invention teaches a method of combining ion metal plasma (IMP) deposition techniques, i.e., with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias “ON”, AC/Rf bias “OFF”, to form both the copper metal diffusion barrier (reactive IMP) and then subsequently, the copper seed layer. The current invention applies to lining both a single and dual damascene structure to form a copper metal barrier layer, TaN, and copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.
Claims42
A method for fabricating integrated circuits on a substrate with single or dual damascene structure, the method comprising:
- providing a substrate or substrate module having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line or conducting region;
- providing a first level of conducting wiring being defined and embedded in a first layer of insulator;
- depositing a second layer of insulator on the first layer of insulator;
- patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;
- depositing on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias On, AC/Rf bias OFF steps and patterning barrier layer;
- depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;
- depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −40 to 40° C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300° C.;
- polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.
A method for fabricating integrated circuits on a substrate with single or dual damascene structure, the method comprising:
- providing a semiconductor substrate or substrate module having a layer of dielectric silicon oxide, interlevel dielectric (ILD), or a copper interconnect line or conducting P-N junction region;
- providing a first level of copper conducting wiring being defined and embedded in a first layer of silicon oxide insulator;
- depositing a second layer of silicon oxide insulator on the first layer of insulator;
- patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;
- deposition on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning barrier layer;
- depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;
- depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −40 to 40° C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300° C.;
- polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.
A method for fabricating MOSFET and CMOS devices on a silicon semiconductor substrate with single or dual damascene structures using electrochemical deposition (ECD) of copper and ion metal plasma (IMP) deposition of copper seed layer and barrier layer, the method comprising:
- providing a semiconductor substrate or substrate module having a layer of dielectric silicon oxide, interlevel dielectric (ILD), or a copper interconnect line or conducting P-N junction region;
- providing a first level of copper conducting wiring being defined and embedded in a first layer of silicon oxide insulator;
- depositing a second layer of silicon oxide insulator on the first layer of insulator;
- patterning and etching the second layer of insulator to form both single and dual damascene trench/via and interconnect structures;
- depositing on the second layer of insulator by reactive ion metal plasma (IMP) a TaN barrier layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning barrier layer;
- depositing on the barrier layer by ion metal plasma (IMP) a copper seed layer with and without AC/Rf bias, in a series of steps or cycles of at least four or more AC/Rf bias ON, AC/Rf bias OFF steps and patterning said seed layer;
- depositing on the copper seed layer by electrochemical deposition (ECD) a copper conducting material by plating copper in a sulfuric acid solution with a solution or plating bath temperature from approximately −40 to 40° C., at a deposition rate of approximately 1,000 Angstroms per minute, forming a copper conducting material thickness from approximately 5,000 to 20,000 Angstroms thick, forming copper grains or crystals from approximately 1,000 to 20,000 Angstroms in size, having a preferred (111) crystal orientation, with a re-crystallization temperature of approximately 100 to 300° C.;
- polishing back by chemical mechanical polishing (CMP) the excess copper conducting material, seed layer, and barrier layer.
Dependencies are inferred from the claim text.