Wafer-level packaging
AssigneeApack Technologies Inc.
InventorTung-Liang Shao
Life of this patent
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Abstract
A wafer-level packaging process. A wafer having a plurality of bonding pads thereon exposed through a passivation layer formed on the wafer is provided, and an under bump metal (UBM) is formed on each bonding pad. A stress buffer layer is formed through which are formed a plurality of first openings that expose the under bump metals (UBM). Solder material is filled in the first openings of the stress buffer layer. Either a stencil or a patterned photoresist having a plurality of second openings is arranged on the stress buffer layer such that the second openings expose the first openings. A solder material is filled in the second openings. The solder material is reflowed, wherein if the stencil is used, it is removed before the reflow process while if the patterned photoresist is used, it is removed after the reflow process.
Claims6
A wafer-level packaging comprising:
- providing a wafer that has a plurality of bonding pads formed thereon, an under bump metal (UBM) being respectively formed on the bonding pads that are exposed through a patterned passivation layer formed on the wafer;
- forming a stress buffer layer that can be patterned on the wafer;
- patterning the stress buffer layer to form a plurality of first openings and cutting paths, the first openings exposing the under bump metals (UBM);
- filling a first solder material in the first openings;
- arranging a mask on the stress buffer layer, wherein the mask has a plurality of second openings communicating with the first openings;
- filling the second openings of the mask with a second solder material;
- and
- reflowing the first and second solder materials to form a plurality of bumps as external connections for the wafer.
Dependencies are inferred from the claim text.