Method of fabricating a semiconductor device

A method of fabricating semiconductor devices, comprising:

• forming a semiconductor substrate of a first conductivity type having an active area, wherein the semiconductor substrate includes a cell region and a peripheral region;
• forming a plurality of gates along a first direction in the cell and peripheral regions;
• forming a first impurity region along at least one gate in the cell region and a second impurity region along at least one gate in the peripheral region;
• forming a first etch-stop layer covering both of the semiconductor substrate and the gates in the peripheral region;
• forming a plurality of plugs in the cell region, wherein the forming a plurality of plugs consists of,
• forming first sidewall spacers at sides of the gates in the cell region,
• forming a first conductive layer between the gates to contact the first impurity region in the cell region and on the etch-stop layer in the peripheral region, and
• forming the plurality of plugs in the cell region by patterning the first conductive layer, wherein the plugs contact the first impurity region in the cell region;
• forming a second sidewall spacers at the sides of the at least one gate to expose the second impurity region in the peripheral region, wherein the second sidewall spacers includes the etch-stop layer;
• forming a heavily-doped impurity region in an exposed part of the second impurity region in the semiconductor substrate in the peripheral region;
• and
• forming an insulating interlayer between the gates where the plugs are not formed.

A method of fabricating semiconductor devices, comprising:

• forming a semiconductor substrate of a first conductivity type having an active area, wherein the semiconductor substrate includes a cell region and a peripheral region;
• forming a plurality of gates along a first direction in the cell and peripheral regions;
• forming a first impurity region along at least one gate in the cell region and a second impurity region along at least one gate in the peripheral region;
• forming a first etch-stop layer covering both of the semiconductor substrate and the gates in the peripheral region and forming first sidewall spacers at sides of the gates in the cell region;
• forming a first conductive layer between the gates to contact the first impurity region in the cell region and on the etch-stop layer in the peripheral region;
• forming a plurality of plugs in the cell region by patterning the first conductive layer, wherein the plugs contact the first impurity region in the cell region;
• forming a second sidewall spacers at the sides of the at least one gate to expose the second impurity region in the peripheral region, wherein the second sidewall spacers includes the etch-stop layer;
• forming a heavily-doped impurity region in an exposed part of the second impurity region in the semiconductor substrate in the peripheral region;
• and
• forming an insulating interlayer between the gates where the plugs are not formed, wherein the forming the insulating interlayer comprises,
• depositing the insulating interlayer, and
• planarizing the insulating interlayer by etching back the insulating interlayer with chemical mechanical polishing to expose the plugs.

A method of fabricating a semiconductor device, comprising:

• forming a semiconductor substrate of a first conductivity type;
• defining an active area by forming a field insulating layer on the substrate;
• forming a plurality of gates along a first direction on the active area, each of the gates includes a gate oxide, a gate electrode on the gate oxide and a first cap insulating layer on the gate electrode;
• forming impurity regions of a second conductive type in an exposed area of the substrate in the active area along sides of the gates;
• forming a plurality of first sidewall spacers on the sides of the gates;
• forming a conductive layer to contact the impurity regions between the gates;
• forming a plurality of first plugs by patterning the conductive layer, wherein each of the first plugs contact a corresponding impurity region, wherein extended portions of some of the first plugs extend onto the field insulating layer;
• forming a first insulating interlayer where the first plugs are not formed between the gates;
• forming a second insulating interlayer on the first cap insulating layer to cover the first plugs and patterning the second insulating interlayer to expose at least one of the extended portions of the first plugs;
• forming a signal lines and a second cap insulating layer on the second insulating interlayer, wherein the signal lines contact the exposed portions of the first plugs;
• exposing the first plugs and forming second sidewalls at sides of the signal lines by etching the second insulating interlayer;
• forming second plugs that contact the exposed first plugs and forming a low resistance layer on the first plugs before the step of forming the second insulating interlayer.

A method of fabricating a semiconductor device, comprising:

• forming a semiconductor substrate of a first conductivity type;
• forming a plurality of gates along a first direction on the semiconductor substrate;
• forming impurity regions of a second conductive type in the substrate along sides of the gates;
• and
• forming a plurality of plugs, wherein the forming a plurality of plugs consists of,
• forming a plurality of sidewall spacers at the sides of the gates,
• forming a conductive layer on the gates, the sidewall spacers and in contact with each of the impurity regions adjacent the gates, and
• forming the plurality of plugs by patterning the conductive layer.