US 6,387,744 B2 · Process for manufacturing semiconductor integrated circuit device

Abstract

A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Claims33

Dependent claims

A method of manufacturing a semiconductor integrated circuit device, comprising:

forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said semiconductor substrate;
introducing a second impurity in said first area by using said first mask to form a second semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a second area within said first area to form a third semiconductor region, serving as a well region, of said second conductivity type in said second semiconductor region;
selectively introducing a fourth impurity in a third area within said first area to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said second semiconductor region;
forming a first MISFET on said third semiconductor region;
and
forming a second MISFET on said fourth semiconductor region.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising:

forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type and exposing a second area located separately from said first area;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposite to said first conductivity type in said substrate, wherein said first impurity is introduced in said second area by using said first mask to form a second semiconductor region of said second semiconductor region of said second conductivity type in said substrate;
introducing a second impurity in said first area by using said first mask to form a third semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said third semiconductor region, wherein said second impurity is introduced in said second area by using said first mask to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said semiconductor substrate such that said fourth semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a third area within said first area to form a fifth semiconductor region, serving as a well region, of said second conductivity type in said third semiconductor region;
and
selectively introducing a fourth impurity in a fourth area within said first area to form a sixth semiconductor region, serving as a well region, of said first conductivity type in said third semiconductor region,
wherein said third impurity and said fourth impurity are not introduced in said second area,
wherein a first MISFET is formed on said fifth semiconductor region,
wherein a second MISFET is formed on said sixth semiconductor region, and
wherein a third MISFET is formed on said fourth semiconductor region.

7 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising:

forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type and exposing a second area located separately from said first area;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said substrate, wherein said first impurity is introduced in said second area by using said first mask to form a second semiconductor region of said second conductivity type in said substrate;
introducing a second impurity in said first area by using said first mask to form a third semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said third semiconductor region, wherein said second impurity is introduced in said second area by using said first mask to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said semiconductor substrate such that said fourth semiconductor region is formed under said second semiconductor region;
and
selectively introducing a third impurity in a third area within said first area to form a fifth semiconductor region, serving as a well region, of said second conductivity type in said third semiconductor region,
wherein said third impurity is not introduced in said second area,
wherein a first MISFET is formed on said fifth semiconductor region,
wherein a second MISFET is formed on said first area except said second area, and
wherein a third MISFET is formed on said fourth semiconductor region.

6 more elements

Dependencies are inferred from the claim text.

Process for manufacturing semiconductor integrated circuit device

Life of this patent

Process for manufacturing semiconductor integrated circuit device

Life of this patent

Abstract

Claims33