Method for adhering and sealing a silicon chip in an integrated circuit package

A process for fabricating an integrated circuit package comprising :

• providing a substrate having an opening extending therethrough to a pair of opposing surfaces of said substrate;
• placing a chip having a pair of opposing major surfaces and a perimeter within said opening in contact with said adhesive material, said chip having a least one bonding pad extending into said opening;
• extending a plurality of routing strips within said substrate to said opening;
• disposing a plurality of pads on a said surface of said substrate;
• electrically connecting at least one of said pads with at least one of said routing strips;
• electrically connecting said routing strips to said at least one bonding pad on said chip with wire bonding;
• disposing an adhesive material on said substrate and within said opening opposed to said chip;
• adhering said chip to said substrate with said adhesive material within said opening;
• and
• heating said chip and said adhesive material to provide an hermetic seal around the perimeter of said chip with said adhesive to protect said chip;
• and
• filling said opening with a potting material;
• further including the steps of:
• disposing at least one bus bar on said substrate;
• electrically connecting said at least one bus bar with at least one of said bonding pads with wire bonding;
• and
• electrically connecting said at least one bus bar with at least one of said pads disposed on said first surface.