Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder
AssigneeTexas Instruments Incorporated
InventorTod D. Wolf
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Abstract
A programmable, reconfigurable Reed-Solomon encoder/decoder allows for flexible reprogramming of encoders and decoders for a variety of applications. The standard Reed-Solomon parameters of the Galois Field order, the primitive polynomial, the number of symbols for each codeword of the transmitted and source data are settable via writable registers. The Reed-Solomon encoder/decoder may be coupled to a digital signal processor which specifies the parameters loaded in the writable registers via data register space of data memory space. The decoder and encoder parameters are separately specified and the decoder and encoder can run simultaneously and independently.
Claims23
A Reed-Solomon encoder/decoder apparatus comprising:
- a decoder setup block having a first writable register storing decode a Galois field order and a second writable register storing an indication of a decode primitive polynomial;
- a decoder block receiving Reed-Solomon coded input data and connected to said decoder setup block, said decoder block decoding said Reed-Solomon coded input data according to said decode Galois field order stored in said first writable register and said indication of a decode primitive polynomial stored in said second writable register, and outputting decoded data;
- an encoder setup block having a third writable register storing an encode Galois field order and a fourth writable register storing an indication of an encode primitive polynomial;
- and
- an encoder block receiving input data and connected to said encoder setup block, said encoder block Reed-Solomon encoding said input data according to said encode Galois field order stored in said third writable register and said indication of an encode primitive polynomial stored in said fourth writable register, and outputting encoded data.
A Reed-Solomon encoder/decoder system comprising:
- a digital signal processor including:
- an arithmetic logic unit for performing addition, subtraction and logical operations,
- an integer multiplier unit,
- a data address generator for generating data addresses within a data address space for data employed by said digital signal processor,
- a program address generator for generating instructions addresses within an instruction address space for program instructions employed by said digital signal processor,
- a memory interface unit connected to said data address generator and said program address generator for accessing an external memory at said data addresses and said instruction addresses, and
- a program control unit responsive to program instructions recalled from a program memory in response to instruction addresses for. controlling operation of said digital signal processor;
- a Reed-Solomon encoder/decoder coprocessor including:
- a decoder setup block having a first writable register storing decode a Galois field order and a second writable register storing an indication of a decode primitive polynomial,
- a decoder block receiving Reed-Solomon coded input data and connected to said decoder setup block, said decoder block decoding said Reed-Solomon coded input data according to said decode Galois field order stored in said first writable register and said indication of a decode primitive polynomial stored in said second writable register, and outputting decoded data,
- an encoder setup block having a third writable register storing an encode Galois field order and a fourth writable register storing an indication of an encode primitive polynomial, and
- an encoder block receiving input data and connected to said encoder setup block, said encoder block Reed-Solomon encoding said input data according to said encode Galois field order stored in said third writable register and said indication of an encode primitive polynomial stored in said fourth writable register, and outputting encoded data.
Dependencies are inferred from the claim text.