Method for performing multiply-add operations on packed data
AssigneeIntel Corporation
InventorsAlexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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AssigneeIntel Corporation
InventorsAlexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
Estimating the term…
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
A computer-implemented method comprising:
In a computer system, a method comprising:
In a computer system having stored therein a first packed data and a second packed data each containing initial data elements, each of said initial data elements in said first packed data having a corresponding initial data element in said second packed data, a method for performing multiply add operations in response to a single instruction, said method comprising the steps of:
In a computer system, a method comprising:
In a computer system, a method comprising:
A computer-implemented method comprising:
In a computer system, a method comprising:
Dependencies are inferred from the claim text.