Semiconductor memory device in which use of cache can be selected

A method of accessing a semiconductor memory device, comprising:

• setting a direct write access mode in response to a direct access internal command and a write internal command;
• setting a direct read access mode in response to said direct access internal command and a read internal command;
• setting an indirect write access mode in response to an indirect access internal command and said write internal command;
• setting an indirect read access mode in response to said indirect access internal command and said read internal command;
• accessing a specific memory cell array such that write data externally supplied is written into said specific memory cell array via a data control circuit, a first bus and a sense amplifier section for said specific memory cell array in said direct write access mode;
• accessing said specific memory cell array such that read data is read out from said specific memory cell array via said sense amplifier section for said specific memory cell array, said first bus, and said data control circuit in said direct read access mode;
• accessing said specific memory cell array such that said write data externally supplied is written into said specific memory cell array via said data control circuit, a second bus, a specific channel memory, a third bus and said sense amplifier section for said specific memory cell array in said indirect write access mode;
• and
• accessing said specific memory cell array such that read data is read out from said specific memory cell array via said sense amplifier section for said specific memory cell array, said third bus, said specific channel memory, said second bus, and said data control circuit in said indirect read access mode.

A data processing system comprising:

• a control unit determining whether or not data processing is to be executed for a data block, generating an external direct access command when it is determined that said data processing is to be executed for said data block, and generating an external indirect access command when it is determined that said data processing is not executed for said data block;
• and
• a semiconductor memory device setting one of an indirect write access mode, an indirect read access mode, a direct write access mode and a direct read access mode based on said external direct access command or said external direct access command, and whether said data processing relates to a write operation or a read operation, and
• wherein said semiconductor memory device comprises:
• a plurality of banks, each of which includes a memory cell array and a sense amplifier section, and a specific one of said plurality of banks for said data block including a specific memory cell array and a specific sense amplifier section;
• a plurality of channel memories;
• a data control circuit;
• a first bus provided between said plurality of banks and said plurality of channel memories;
• a second bus provided between said plurality of channel memories and said data control circuit;
• and
• a third bus between said plurality of banks and said data control circuit, and
• wherein said data control circuit sends first write data of said data block from said control unit to said specific sense amplifier section via said third bus in said direct write access mode, receives first read data of said data block from said specific sense amplifier section via said third bus in said direct read access mode, sends second write data to said sense amplifier section of a specified one of said plurality of banks via said second bus, a specified one of said plurality of channel memories and said first bus in said indirect write access mode, and receives second read data from said sense amplifier section of a specified one of said plurality of banks via said first bus, a specified one of said plurality of channel memories and said second bus in said indirect read access mode.