DRAM capable of selectively performing self-refresh operation for memory bank

A dynamic random access memory (DRAM) comprising:

• a plurality of individually-accessible memory banks;
• a plurality of voltage generators corresponding to each of the respective memory banks, for supplying internal voltages to the respective memory banks;
• and
• a self-refresh controller for selectively performing a self-refresh operation for one or more memory banks among the plurality of memory banks during the self-refresh operation;
• wherein the voltage generators are selectively enabled according to whether the self-refresh operation is to be performed with respect to the corresponding memory banks, and
• wherein a selection control signal distinguishes active memory banks from inactive memory banks, wherein the self-refresh operation is performed exclusively on the active memory banks, and wherein the inactive memory banks are dormant during the self-refresh operation of the active memory banks.

A dynamic random access memory (DRAM) including a plurality of memory banks, each memory bank having a plurality of memory cells arranged in columns and rows, wherein the DRAM is capable of selectively refreshing data stored in each memory bank during operation in a self-refresh mode, the DRAM comprising:

• a plurality of row decoders for selecting word lines of the memory cells in the memory banks;
• an address generator for generating internal addresses which sequentially vary during the self-refresh mode;
• a self-refresh bank designating circuit for selectively generating self-refresh bank designating signals for designating a memory bank to be refreshed in a self-refresh operation;
• and
• a bank selection decoder for designating one or more memory banks, among the plurality of the memory banks to be refreshed by the self-refresh bank designating signals and for supplying self-refresh addresses to the row decoders corresponding to the designated memory banks according to the internal addresses;
• wherein the self-refresh designating signals distinguish active memory banks from inactive memory banks, wherein the self-refresh operation is performed exclusively on the active memory banks, and wherein the inactive memory banks are dormant during the self-refresh operation of the active memory banks.

A dynamic random access memory (DRAM) comprising:

• a plurality of memory banks capable of being independently accessed;
• a plurality of voltage generators corresponding to the respective memory banks, for supplying internal voltages to the memory banks;
• and
• a self-refresh controller for selectively performing a self-refresh operation for one or more memory banks among the plurality of memory banks during the self-refresh operation;
• wherein the number of enabled voltage generators is determined by the number of memory banks undergoing the self-refresh operations;
• wherein a selection control signal distinguishes active memory banks from inactive memory banks, wherein the self-refresh operation is performed exclusively on the active memory banks, and wherein the inactive memory banks are dormant during the self-refresh operation of the active memory banks.

A dynamic random access memory (DRAM) including a plurality of memory banks, each memory bank having a plurality of memory cells arranged in columns and rows, wherein the DRAM is capable of selectively refreshing data stored in each memory bank during operation in a self-refresh mode, the DRAM comprising:

• a plurality of row decoders for selecting word lines of the memory cells in the memory banks;
• an address generator for generating internal addresses which sequentially vary during the self-refresh mode;
• a self-refresh bank designating circuit for generating self-refresh bank designating signals for designating a memory bank to be refreshed in a self-refresh operation, the self-refresh bank designating circuit comprising:
• a self-refresh controller including control fuses for generating self-refresh control signals in response to a state of the control fuses, the self-refresh controller for controlling selection of the memory banks to be refreshed, and a decoder for decoding the self-refresh control signals to generate the self-refresh bank designating signals;
• and
• a bank selection decoder for designating one or more memory banks among the plurality of memory banks to be refreshed by the refresh bank designating signals and for supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the internal addresses;
• wherein the self-refresh bank designating signals distinguish active memory banks from inactive memory banks, wherein the self-refresh operation is performed exclusively on the active memory banks, and wherein the inactive memory banks are dormant during the self-refresh operation of the active memory banks.